From patchwork Thu Mar 29 11:04:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manu Gautam X-Patchwork-Id: 10314925 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8748C60353 for ; Thu, 29 Mar 2018 11:06:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7ED312A319 for ; Thu, 29 Mar 2018 11:06:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B9622A301; Thu, 29 Mar 2018 11:06:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A3EA32A301 for ; Thu, 29 Mar 2018 11:06:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751195AbeC2LGz (ORCPT ); Thu, 29 Mar 2018 07:06:55 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:43984 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752695AbeC2LGw (ORCPT ); Thu, 29 Mar 2018 07:06:52 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7C81560C67; Thu, 29 Mar 2018 11:06:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522321611; bh=y0Kax9TH2jeOWtyhzoNHa922r0ktrC6HS7tlFdb+VIU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SFbtMmNYOKeVhfeg2hcycvldifvpdlDofFmCeFfOX4Y75yksPFM30dCHA3/SBfDuc 0VxYG0FtEB82614kPmvA/x+IdzTSzYJBEA6jKx1zNgUljP30s24zRQL7Ht+qUyAxKW W13fVTQj0W+e9NZqdxyVefpzP19dcDwH1Stha8xI= Received: from mgautam-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mgautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 41DB260BFA; Thu, 29 Mar 2018 11:06:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522321610; bh=y0Kax9TH2jeOWtyhzoNHa922r0ktrC6HS7tlFdb+VIU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YtOpi1Sbn0e8sLi0na34hVHDmzl3iflvykPn0D5CcVKGxh2azziA72Oevc1nr5AQM e6jXFwmfZF0v1ZQYdAXXc3XJSsvdvmplKNsq+x0AfZpTFB8Wo8zt3pUOvXV3aoqAPc 4WEwcGXRP4cnaLrz6g9DbgnbMo05sGQGGCnYG+U8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 41DB260BFA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=mgautam@codeaurora.org From: Manu Gautam To: Kishon Vijay Abraham I , robh@kernel.org, sboyd@codeaurora.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, vivek.gautam@codeaurora.org, evgreen@chromium.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, Manu Gautam , Viresh Kumar Subject: [PATCH v4 7/7] phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845 Date: Thu, 29 Mar 2018 16:34:26 +0530 Message-Id: <1522321466-21755-8-git-send-email-mgautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522321466-21755-1-git-send-email-mgautam@codeaurora.org> References: <1522321466-21755-1-git-send-email-mgautam@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are two QUSB2 PHYs present on sdm845. In order to improve eye diagram for both the PHYs some parameters need to be changed. Provide device tree properties to override these from board specific device tree files. Signed-off-by: Manu Gautam --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 112 +++++++++++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index 40fdef8..adcc3f8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -60,6 +60,17 @@ #define CORE_RESET BIT(5) #define CORE_RESET_MUX BIT(6) +/* QUSB2PHY_IMP_CTRL1 register bits */ +#define IMP_RES_OFFSET_MASK GENMASK(5, 0) +#define IMP_RES_OFFSET_SHIFT 0x0 + +/* QUSB2PHY_PORT_TUNE1 register bits */ +#define HSTX_TRIM_MASK GENMASK(7, 4) +#define HSTX_TRIM_SHIFT 0x4 +#define PREEMPH_HALF_WIDTH BIT(2) +#define PREEMPHASIS_EN_MASK GENMASK(1, 0) +#define PREEMPHASIS_EN_SHIFT 0x0 + #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c #define QUSB2PHY_PLL_CMODE 0x2c @@ -241,6 +252,18 @@ struct qusb2_phy_cfg { * @tcsr: TCSR syscon register map * @cell: nvmem cell containing phy tuning value * + * @override_imp_res_offset: PHY should use different rescode offset + * @imp_res_offset_value: rescode offset to be updated in IMP_CTRL1 register + * + * @override_hstx_trim: PHY should use different HSTX o/p current value + * @hstx_trim_value: HSTX_TRIM value to be updated in TUNE1 register + * + * @override_preemphasis: PHY should use different pre-amphasis amplitude + * @preemphasis_level: Amplitude Pre-Emphasis to be updated in TUNE1 register + * + * @override_preemphasis_width: PHY should use different pre-emphasis duration + * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1 + * * @cfg: phy config data * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme * @phy_initialized: indicate if PHY has been initialized @@ -259,12 +282,35 @@ struct qusb2_phy { struct regmap *tcsr; struct nvmem_cell *cell; + bool override_imp_res_offset; + u8 imp_res_offset_value; + bool override_hstx_trim; + u8 hstx_trim_value; + bool override_preemphasis; + u8 preemphasis_level; + bool override_preemphasis_width; + u8 preemphasis_width; + const struct qusb2_phy_cfg *cfg; bool has_se_clk_scheme; bool phy_initialized; enum phy_mode mode; }; +static inline void qusb2_write_mask(void __iomem *base, u32 offset, + u32 val, u32 mask) +{ + u32 reg; + + reg = readl(base + offset); + reg &= ~mask; + reg |= val; + writel(reg, base + offset); + + /* Ensure above write is completed */ + readl(base + offset); +} + static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) { u32 reg; @@ -305,6 +351,42 @@ void qcom_qusb2_phy_configure(void __iomem *base, } /* + * Update board specific PHY tuning override values if specified from + * device tree. + * + */ +static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy) +{ + const struct qusb2_phy_cfg *cfg = qphy->cfg; + + if (qphy->override_imp_res_offset) + qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, + qphy->imp_res_offset_value << IMP_RES_OFFSET_SHIFT, + IMP_RES_OFFSET_MASK); + + if (qphy->override_hstx_trim) + qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], + qphy->hstx_trim_value << HSTX_TRIM_SHIFT, + HSTX_TRIM_MASK); + + if (qphy->override_preemphasis) + qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], + qphy->preemphasis_level << PREEMPHASIS_EN_SHIFT, + PREEMPHASIS_EN_MASK); + + if (qphy->override_preemphasis_width) { + if (qphy->preemphasis_width) + qusb2_setbits(qphy->base, + cfg->regs[QUSB2PHY_PORT_TUNE1], + PREEMPH_HALF_WIDTH); + else + qusb2_clrbits(qphy->base, + cfg->regs[QUSB2PHY_PORT_TUNE1], + PREEMPH_HALF_WIDTH); + } +} + +/* * Fetches HS Tx tuning value from nvmem and sets the * QUSB2PHY_PORT_TUNE1/2 register. * For error case, skip setting the value and use the default value. @@ -525,6 +607,9 @@ static int qusb2_phy_init(struct phy *phy) qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, cfg->tbl_num); + /* Override board specific PHY tuning values */ + qusb2_phy_override_phy_params(qphy); + /* Set efuse value for tuning the PHY */ qusb2_phy_set_tune2_param(qphy); @@ -647,7 +732,7 @@ static int qusb2_phy_exit(struct phy *phy) .compatible = "qcom,msm8996-qusb2-phy", .data = &msm8996_phy_cfg, }, { - .compatible = "qcom,qusb2-v2-phy", + .compatible = "qcom,sdm845-qusb2-phy", .data = &qusb2_v2_phy_cfg, }, { }, @@ -736,6 +821,31 @@ static int qusb2_phy_probe(struct platform_device *pdev) qphy->cell = NULL; dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); } + + if (of_find_property(dev->of_node, "qcom,imp-res-offset-value", NULL)) { + qphy->override_imp_res_offset = true; + of_property_read_u8(dev->of_node, "qcom,imp-res-offset-value", + &qphy->imp_res_offset_value); + } + + if (of_find_property(dev->of_node, "qcom,hstx-trim-value", NULL)) { + qphy->override_hstx_trim = true; + of_property_read_u8(dev->of_node, "qcom,hstx-trim-value", + &qphy->hstx_trim_value); + } + + if (of_find_property(dev->of_node, "qcom,preemphasis-level", NULL)) { + qphy->override_preemphasis = true; + of_property_read_u8(dev->of_node, "qcom,preemphasis-level", + &qphy->preemphasis_level); + } + + if (of_find_property(dev->of_node, "qcom,preemphasis-width", NULL)) { + qphy->override_preemphasis_width = true; + of_property_read_u8(dev->of_node, "qcom,preemphasis-width", + &qphy->preemphasis_width); + } + pm_runtime_set_active(dev); pm_runtime_enable(dev); /*