From patchwork Thu Mar 29 21:26:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilia Lin X-Patchwork-Id: 10316273 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 52BEF60383 for ; Thu, 29 Mar 2018 21:27:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3477E2A0DA for ; Thu, 29 Mar 2018 21:27:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 28EDE2A0E2; Thu, 29 Mar 2018 21:27:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE3342A0DA for ; Thu, 29 Mar 2018 21:27:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752568AbeC2V1r (ORCPT ); Thu, 29 Mar 2018 17:27:47 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:34338 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751189AbeC2V1n (ORCPT ); Thu, 29 Mar 2018 17:27:43 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CCC4A60FF0; Thu, 29 Mar 2018 21:27:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522358861; bh=8vbCGJXVzh+0qm7ObeCQvLCP1S+SCg4vm2dCzFK11E4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RCBBrHTlH8mD4LVO8V2Uncv/wcPL9PtqkvtUk1+bOhlrxvDJgH8SYBfbk7zYHpdXA ZewDYMBPE0B/rhkd2n/n7xHny3qdjENlb9rALPvxyFYWhdZ8nBj7sM7NnoVeIrs+jB voE2uzi6Xebk+IcMoBIKep0CMevUIZZ9q0hNfmhs= Received: from lx-ilial.mea.qualcomm.com (unknown [185.23.60.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilialin@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 99E6B60AFB; Thu, 29 Mar 2018 21:27:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522358853; bh=8vbCGJXVzh+0qm7ObeCQvLCP1S+SCg4vm2dCzFK11E4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RDchJbKRGPD21yZcg5HtxWs1wOfGD7xM3fP843af8JNhbhrNEoBrciHinUIZxhLMo dISCpVs5s2Il0VA2LFUHxHim4Yqrb4uoT/mNOqE7aY8JtdZqoW9cX0p9dJ7bwY6OGQ hfK2vbRAl5JVPutTQiGbyjFlxm8bXmASN2N6aIYA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 99E6B60AFB Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilialin@codeaurora.org From: Ilia Lin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, viresh.kumar@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, andy.gross@linaro.org, david.brown@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: rnayak@codeaurora.org, ilialin@codeaurora.org, amit.kucheria@linaro.org, nicolas.dechesne@linaro.org, celster@codeaurora.org, tfinkel@codeaurora.org Subject: [PATCH v4 06/14] clk: qcom: cpu-8996: Add support to switch below 600Mhz Date: Fri, 30 Mar 2018 00:26:39 +0300 Message-Id: <1522358807-10413-7-git-send-email-ilialin@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522358807-10413-1-git-send-email-ilialin@codeaurora.org> References: <1522358807-10413-1-git-send-email-ilialin@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rajendra Nayak The CPU clock controller's primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. So for frequencies above 600MHz we follow the following path Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk and for frequencies between 300MHz and 600MHz we follow Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk Signed-off-by: Rajendra Nayak Signed-off-by: Ilia Lin Conflicts: drivers/clk/qcom/clk-cpu-8996.c --- drivers/clk/qcom/clk-cpu-8996.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 12585b1..064a3fe 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -78,6 +78,8 @@ enum _pmux_input { NUM_OF_PMUX_INPUTS }; +#define DIV_2_THRESHOLD 600000000 + static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { [PLL_OFF_L_VAL] = 0x04, [PLL_OFF_ALPHA_VAL] = 0x08, @@ -105,10 +107,11 @@ enum _pmux_input { static const struct alpha_pll_config hfpll_config = { .l = 60, - .config_ctl_val = 0x200d4828, + .config_ctl_val = 0x200d4aa8, .config_ctl_hi_val = 0x006, .pre_div_mask = BIT(12), .post_div_mask = 0x3 << 8, + .post_div_val = 0x1 << 8, .main_output_mask = BIT(0), .early_output_mask = BIT(3), }; @@ -150,7 +153,7 @@ enum _pmux_input { .vco_mask = 0x3 << 20, .config_ctl_val = 0x4001051b, .post_div_mask = 0x3 << 8, - .post_div_val = 0x1, + .post_div_val = 0x1 << 8, .main_output_mask = BIT(0), .early_output_mask = BIT(3), }; @@ -191,6 +194,7 @@ struct clk_cpu_8996_mux { u8 width; struct notifier_block nb; struct clk_hw *pll; + struct clk_hw *pll_div_2; struct clk_regmap clkr; }; @@ -236,6 +240,13 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); struct clk_hw *parent = cpuclk->pll; + if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) { + if (req->rate < (DIV_2_THRESHOLD / 2)) + return -EINVAL; + + parent = cpuclk->pll_div_2; + } + req->best_parent_rate = clk_hw_round_rate(parent, req->rate); req->best_parent_hw = parent; @@ -247,13 +258,19 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, { int ret; struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb); + struct clk_notifier_data *cnd = data; switch (event) { case PRE_RATE_CHANGE: ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); break; case POST_RATE_CHANGE: - ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX); + if (cnd->new_rate < DIV_2_THRESHOLD) + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, + DIV_2_INDEX); + else + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, + PLL_INDEX); break; default: ret = 0; @@ -305,6 +322,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, + .pll_div_2 = &pwrcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", @@ -325,6 +343,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, + .pll_div_2 = &perfcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux",