From patchwork Tue Nov 20 11:37:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 10690299 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C73B55A4 for ; Tue, 20 Nov 2018 11:37:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B7D802906E for ; Tue, 20 Nov 2018 11:37:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AC2652A7F2; Tue, 20 Nov 2018 11:37:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A0CDD2906E for ; Tue, 20 Nov 2018 11:37:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729320AbeKTWGb (ORCPT ); Tue, 20 Nov 2018 17:06:31 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:46556 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729099AbeKTWGb (ORCPT ); Tue, 20 Nov 2018 17:06:31 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id ED34F60C4C; Tue, 20 Nov 2018 11:37:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1542713867; bh=9paNBs/GY8l+ygBBU69XNYjcXGkdL7RsBOT0NAuuQaI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lRYCPVauPewXlslYeh9NZM2NTnTJMrLhyetseNB+NbB2fuWT3Rrc9LbvouupfklgC DYTgj/LNSVAxuvT3jKjFRnP/FnRc4Ix22jhkfjt4/8V1DM1sj6EzdwSDgNmvPo2OWU uw5IXz56fdled+95dYc63U3NvplFl7XG7SoE+hJg= Received: from smasetty-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4C66160B7A; Tue, 20 Nov 2018 11:37:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1542713867; bh=9paNBs/GY8l+ygBBU69XNYjcXGkdL7RsBOT0NAuuQaI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lRYCPVauPewXlslYeh9NZM2NTnTJMrLhyetseNB+NbB2fuWT3Rrc9LbvouupfklgC DYTgj/LNSVAxuvT3jKjFRnP/FnRc4Ix22jhkfjt4/8V1DM1sj6EzdwSDgNmvPo2OWU uw5IXz56fdled+95dYc63U3NvplFl7XG7SoE+hJg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4C66160B7A Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, jcrouse@codeaurora.org, Sharat Masetty Subject: [PATCH 3/4] drm/msm: Use msm_gpu_state_bo for ringbuffer data Date: Tue, 20 Nov 2018 17:07:30 +0530 Message-Id: <1542713851-14375-3-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542713851-14375-1-git-send-email-smasetty@codeaurora.org> References: <1542713851-14375-1-git-send-email-smasetty@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The ring substructure in msm_gpu_state is an extension of msm_gpu_state_bo, so this patch changes the ring structure to reuse the msm_gpu_state_bo as a base class, instead of redefining the required variables. Signed-off-by: Sharat Masetty Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 20 +++++++++++--------- drivers/gpu/drm/msm/msm_gpu.h | 4 +--- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 6ebe842..bbf8d3e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -383,7 +383,7 @@ int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) int size = 0, j; state->ring[i].fence = gpu->rb[i]->memptrs->fence; - state->ring[i].iova = gpu->rb[i]->iova; + state->ring[i].bo.iova = gpu->rb[i]->iova; state->ring[i].seqno = gpu->rb[i]->seqno; state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); state->ring[i].wptr = get_wptr(gpu->rb[i]); @@ -397,10 +397,12 @@ int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) size = j + 1; if (size) { - state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL); - if (state->ring[i].data) { - memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2); - state->ring[i].data_size = size << 2; + state->ring[i].bo.data = + kvmalloc(size << 2, GFP_KERNEL); + if (state->ring[i].bo.data) { + memcpy(state->ring[i].bo.data, + gpu->rb[i]->start, size << 2); + state->ring[i].bo.size = size << 2; } } } @@ -440,7 +442,7 @@ void adreno_gpu_state_destroy(struct msm_gpu_state *state) int i; for (i = 0; i < ARRAY_SIZE(state->ring); i++) - kvfree(state->ring[i].data); + kvfree(state->ring[i].bo.data); for (i = 0; state->bos && i < state->nr_bos; i++) kvfree(state->bos[i].data); @@ -522,15 +524,15 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, for (i = 0; i < gpu->nr_rings; i++) { drm_printf(p, " - id: %d\n", i); - drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova); + drm_printf(p, " iova: 0x%016llx\n", state->ring[i].bo.iova); drm_printf(p, " last-fence: %d\n", state->ring[i].seqno); drm_printf(p, " retired-fence: %d\n", state->ring[i].fence); drm_printf(p, " rptr: %d\n", state->ring[i].rptr); drm_printf(p, " wptr: %d\n", state->ring[i].wptr); drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ); - adreno_show_object(p, state->ring[i].data, - state->ring[i].data_size); + adreno_show_object(p, state->ring[i].bo.data, + state->ring[i].bo.size); } if (state->bos) { diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 7dc775f..a3a6371 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -198,13 +198,11 @@ struct msm_gpu_state { struct timeval time; struct { - u64 iova; u32 fence; u32 seqno; u32 rptr; u32 wptr; - void *data; - int data_size; + struct msm_gpu_state_bo bo; } ring[MSM_GPU_MAX_RINGS]; int nr_registers;