From patchwork Tue Jan 29 23:58:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10787363 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 49FDF1399 for ; Tue, 29 Jan 2019 23:58:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2F64B2C535 for ; Tue, 29 Jan 2019 23:58:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2345D2C583; Tue, 29 Jan 2019 23:58:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AF4462C535 for ; Tue, 29 Jan 2019 23:58:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727148AbfA2X6k (ORCPT ); Tue, 29 Jan 2019 18:58:40 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:37564 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726954AbfA2X6k (ORCPT ); Tue, 29 Jan 2019 18:58:40 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 13E74607F4; Tue, 29 Jan 2019 23:58:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548806319; bh=TFeXFeJqUiZeXmdhfW4qtXXuxyR/0wVRifb6XPiV5Qo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UhHvXy/hbi9gAihM21fU3/zLhkzeZqnSEfokKW0f3/A7Pr7g3AGNbKMVrgQDLqqoa N6jJcKhwDrD9pEOu5zprbu4YaXO8IuK7JntwqgET+53qd+geuJMwkrQtBY6OjKECWG rq/GjDBwB7DbtyuATCNfPM8Yt16H3QhaUQeNN4WU= Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A89D8602F8; Tue, 29 Jan 2019 23:58:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548806318; bh=TFeXFeJqUiZeXmdhfW4qtXXuxyR/0wVRifb6XPiV5Qo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GVonx3/teCd98QitGqH9AgSQZBsu3DkylPL/3CdaphdurKJ5A64d8f/cLUOkERi/J RzsPiZ/H1PmXjmI2O9yJ/LVqNsewc9A7CcLsFfdYiXMf08UYErH6+PNdY1eiOgkOHX ASRBRQpCuX1piDy9G/KUSI3fCG1JI7dkoz97uHJY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A89D8602F8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: srinivas.kandagatla@linaro.org Cc: andy.gross@linaro.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, vivek.gautam@codeaurora.org Subject: [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions Date: Tue, 29 Jan 2019 16:58:34 -0700 Message-Id: <1548806314-31788-1-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <20190129132335.30695-5-srinivas.kandagatla@linaro.org> References: <20190129132335.30695-5-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add an initial node for the Adreno GPU and it's companion SMMU. Signed-off-by: Vivek Gautam Signed-off-by: Srinivas Kandagatla Signed-off-by: Jordan Crouse --- This is slightly updated version of [1] to include a correct OPP table and other such stuff. I didn't know the best way to send it, so I attached it to the original email and hopefully Andy forgives me. Otherwise, Srinivas can resend it correctly. [1] https://patchwork.kernel.org/patch/10786185/ arch/arm64/boot/dts/qcom/msm8996.dtsi | 86 +++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 0d0b948..0950415 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -84,6 +84,12 @@ qcom,client-id = <1>; qcom,vmid = <15>; }; + + zap_shader_region: gpu@8f200000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x90b00000 0x0 0xa00000>; + no-map; + }; }; cpus { @@ -796,6 +802,11 @@ reg = <0x24f 0x1>; bits = <1 4>; }; + + gpu_speed_bin: gpu_speed_bin@133 { + reg = <0x133 0x1>; + bits = <5 3>; + }; }; phy@34000 { @@ -1338,6 +1349,81 @@ }; }; + gpu@b00000 { + compatible = "qcom,adreno-530.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0xb00000 0x3f000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc GPU_GX_GFX3D_CLK>, + <&mmcc GPU_AHB_CLK>, + <&mmcc GPU_GX_RBBMTIMER_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_MMSS_BIMC_GFX_CLK>; + + clock-names = "core", + "iface", + "rbbmtimer", + "mem", + "mem_iface"; + + power-domains = <&mmcc GPU_GDSC>; + iommus = <&adreno_smmu 0>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + qcom,gpu-quirk-two-pass-use-wfi; + qcom,gpu-quirk-fault-detect-mask; + + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp-table { + compatible ="operating-points-v2"; + + /* + * 624Mhz and 560Mhz are only available on speed + * bin (1 << 0). All the rest are available on + * all bins of the hardware + */ + opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-supported-hw = <0x01>; + }; + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-supported-hw = <0x01>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-supported-hw = <0xFF>; + }; + opp-401800000 { + opp-hz = /bits/ 64 <401800000>; + opp-supported-hw = <0xFF>; + }; + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-supported-hw = <0xFF>; + }; + opp-214000000 { + opp-hz = /bits/ 64 <214000000>; + opp-supported-hw = <0xFF>; + }; + opp-133000000 { + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0xFF>; + }; + }; + + zap-shader { + memory-region = <&zap_shader_region>; + }; + }; + mdss: mdss@900000 { compatible = "qcom,mdss";