From patchwork Tue Apr 28 13:33:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 11514729 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A18CB1575 for ; Tue, 28 Apr 2020 13:39:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8A80D206D6 for ; Tue, 28 Apr 2020 13:39:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="eFwaekdC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728077AbgD1Njx (ORCPT ); Tue, 28 Apr 2020 09:39:53 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:49790 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726898AbgD1Njw (ORCPT ); Tue, 28 Apr 2020 09:39:52 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1588081192; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=MkGLn7lkOqxZllVszXuo1Fr40qbxDQiMjGnb44dbThE=; b=eFwaekdC69U0LXR1Zgczk1bOgaUePPY5Ho+wJoM55pGSLUfacmTlkf3lroyDFWg0w13Uqfq0 PbmqEx818PJZciSTjAwspZS8qxzbZOXxdrrIxfY2BQIOu11uyBXjJI40fBp0/uVEvQcJN6mJ BN1jB+TVAqeg/Szfr5F9e2srWVc= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5ea83223.7f0f29d61260-smtp-out-n01; Tue, 28 Apr 2020 13:39:47 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id D4B3AC690A4; Tue, 28 Apr 2020 13:39:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak) by smtp.codeaurora.org (Postfix) with ESMTPSA id 47E26C0451C; Tue, 28 Apr 2020 13:39:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 47E26C0451C Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: viresh.kumar@linaro.org, sboyd@kernel.org, bjorn.andersson@linaro.org, agross@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, Rajendra Nayak Subject: [PATCH v3 17/17] arm64: dts: sc7180: Add qspi opps and power-domains Date: Tue, 28 Apr 2020 19:03:05 +0530 Message-Id: <1588080785-6812-18-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1588080785-6812-1-git-send-email-rnayak@codeaurora.org> References: <1588080785-6812-1-git-send-email-rnayak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the power domain supporting performance state and the corresponding OPP tables for the qspi device on sc7180 Signed-off-by: Rajendra Nayak --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index b87f3eb..c340a63 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1421,6 +1421,25 @@ #power-domain-cells = <1>; }; + qspi_opp_table: qspi-opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + qspi: spi@88dc000 { compatible = "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; @@ -1430,6 +1449,8 @@ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", "core"; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qspi_opp_table>; status = "disabled"; };