From patchwork Fri Aug 21 09:30:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hsin-Hsiung Wang X-Patchwork-Id: 11728691 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AF7621575 for ; Fri, 21 Aug 2020 09:31:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 95DAF207DE for ; Fri, 21 Aug 2020 09:31:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Z+vwNJnJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728101AbgHUJbL (ORCPT ); Fri, 21 Aug 2020 05:31:11 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:3227 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725965AbgHUJbK (ORCPT ); Fri, 21 Aug 2020 05:31:10 -0400 X-UUID: f4295ce883d44d24b6e236211704ced1-20200821 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=CzHYYkmPwpQ2AhKcg65BgQbtfesFRKYUwxvX0kNJpAM=; b=Z+vwNJnJh0nwVwgVSj9g3M3ZE4gowtox6pVfQ0ckqWPUsVnD4KV0yh/WUHGQy/YhXvKEc3j14+9COxECsIA3O1JfHuHkCSwj8L4CHyVTbeRrvH422yeC0HO8664hFof6UTwRjn9MqkCt9ZhLHZGExE+Wv6CsMPSy2jmDwH62hAA=; X-UUID: f4295ce883d44d24b6e236211704ced1-20200821 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 113662065; Fri, 21 Aug 2020 17:31:05 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 21 Aug 2020 17:31:02 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 21 Aug 2020 17:31:02 +0800 From: Hsin-Hsiung Wang To: Stephen Boyd , Rob Herring , Matthias Brugger CC: Hsin-Hsiung Wang , , , , , , Subject: [PATCH 1/2] dt-bindings: spmi: document binding for the Mediatek SPMI controller Date: Fri, 21 Aug 2020 17:30:59 +0800 Message-ID: <1598002260-12724-2-git-send-email-hsin-hsiung.wang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1598002260-12724-1-git-send-email-hsin-hsiung.wang@mediatek.com> References: <1598002260-12724-1-git-send-email-hsin-hsiung.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This adds documentation for the SPMI controller found on Mediatek SoCs. Signed-off-by: Hsin-Hsiung Wang --- .../devicetree/bindings/spmi/spmi-mtk-pmif.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.txt diff --git a/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.txt b/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.txt new file mode 100644 index 0000000..75a0eeb --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.txt @@ -0,0 +1,33 @@ +Mediatek SPMI Controller + +This document describes the binding for the MediaTek SPMI controller. + +On MediaTek SoCs the PMIC is connected via SPMI and the controller allows +for multiple SoCs to control a single SPMI master. + +Required properties: +- compatible : "mediatek,mt6873-spmi". +- reg-names : must contain: + "pmif" - pmif registers + "spmimst" - spmi controller registers +- reg: Must contain an entry for each entry in reg-names. +- clock-names: Must include the following entries: + "pmif_sys_ck": pmif system clock + "pmif_tmr_ck": pmif timer clock + "spmimst_clk_mux": spmi master clk mux +- clocks: Must contain an entry for each entry in clock-names. + +Example: + + spmi: spmi@10027000 { + compatible = "mediatek,mt6873-spmi"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + };