From patchwork Thu Oct 15 12:59:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hsin-Hsiung Wang X-Patchwork-Id: 11839289 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 211A361C for ; Thu, 15 Oct 2020 12:59:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F25D82225C for ; Thu, 15 Oct 2020 12:59:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="OytQrD+T" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727845AbgJOM7U (ORCPT ); Thu, 15 Oct 2020 08:59:20 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:43774 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726121AbgJOM7R (ORCPT ); Thu, 15 Oct 2020 08:59:17 -0400 X-UUID: 29e54caaea214e3e820ff043186704ec-20201015 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FLPCDUAskVZvAtsDNHb6TvCzZkL8/uiNYJKOELwOJe8=; b=OytQrD+TYHcHcEvIsoFkxMmwDUTsNn56+6hxSGFc2aLX7cu29kmdrhvEvhea8PSCxQoNzNDZoYSlixzQEInuYhgE4+VCY/0Rjk+2O26IoUA2xFbw9PYkUVC8x9edrycjkgo8yP0gdMEi+Vox5E3QLRZq5znXygXSqtNPBFJRxIg=; X-UUID: 29e54caaea214e3e820ff043186704ec-20201015 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 780969323; Thu, 15 Oct 2020 20:59:11 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 15 Oct 2020 20:59:09 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 15 Oct 2020 20:59:09 +0800 From: Hsin-Hsiung Wang To: Stephen Boyd , Rob Herring , Matthias Brugger CC: Hsin-Hsiung Wang , , , , , , Subject: [PATCH v3 1/2] dt-bindings: spmi: document binding for the Mediatek SPMI controller Date: Thu, 15 Oct 2020 20:59:07 +0800 Message-ID: <1602766748-25490-2-git-send-email-hsin-hsiung.wang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1602766748-25490-1-git-send-email-hsin-hsiung.wang@mediatek.com> References: <1602766748-25490-1-git-send-email-hsin-hsiung.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This adds documentation for the SPMI controller found on Mediatek SoCs. Signed-off-by: Hsin-Hsiung Wang --- .../bindings/spmi/spmi-mtk-pmif.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.yaml diff --git a/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.yaml new file mode 100644 index 000000000000..39459ca2e0da --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/spmi-mtk-pmif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek SPMI Controller Device Tree Bindings + +maintainers: + - Stephen Boyd + - Matthias Brugger + +description: |+ + On MediaTek SoCs the PMIC is connected via SPMI and the controller allows + for multiple SoCs to control a single SPMI master. + +properties: + compatible: + const: mediatek,mt6873-spmi + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: "pmif" + - const: "spmimst" + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: "pmif_sys_ck" + - const: "pmif_tmr_ck" + - const: "spmimst_clk_mux" + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +examples: + - | + #include + + spmi: spmi@10027000 { + compatible = "mediatek,mt6873-spmi"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; +...