From patchwork Sun Oct 24 10:09:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 12580159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E210C433F5 for ; Sun, 24 Oct 2021 10:09:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EFBA560C41 for ; Sun, 24 Oct 2021 10:09:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231154AbhJXKMG (ORCPT ); Sun, 24 Oct 2021 06:12:06 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:56739 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231138AbhJXKMF (ORCPT ); Sun, 24 Oct 2021 06:12:05 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1635070185; h=Message-Id: Date: Subject: Cc: To: From: Sender; bh=uPM/FEmwfm4Sj6+7q4K5x9KDl5H8MzbhJyLMihXVIE8=; b=CbbG2UEZYsTEAFVONDYX8C1clAKIONCfM1lE7iTaBulg2sekwWFj7L4S+NtazviGjinbB+dy XB2ACyAN/zJjzM3KcgGgb7f9FTs1YEZvOJzt6sFZ+u2kmXpivJc9Zk4nyi9kcWoLdTx+Dyxo 617nlWs4BWigk2OLV1qnmb/jBTg= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-east-1.postgun.com with SMTP id 617530de8e67b5f04e2b26e7 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Sun, 24 Oct 2021 10:09:34 GMT Sender: tdas=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 0DA81C4360D; Sun, 24 Oct 2021 10:09:34 +0000 (UTC) Received: from tdas-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: tdas) by smtp.codeaurora.org (Postfix) with ESMTPSA id 69F4CC4338F; Sun, 24 Oct 2021 10:09:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org 69F4CC4338F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=codeaurora.org From: Taniya Das To: Rob Herring , Bjorn Andersson Cc: Douglas Anderson , Stephen Boyd , Andy Gross , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das Subject: [PATCH] arm64: dts: qcom: sc7280: Add camcc clock node Date: Sun, 24 Oct 2021 15:39:22 +0530 Message-Id: <1635070162-21669-1-git-send-email-tdas@codeaurora.org> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the camera clock controller node for SC7280 SoC. Also add the header file for lpass clock controller. Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation. diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d74a4c8..8e6b011 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4,10 +4,11 @@ * * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ - +#include #include #include #include +#include #include #include #include @@ -2570,6 +2571,18 @@ #power-domain-cells = <1>; }; + camcc: clock-controller@ad00000 { + compatible = "qcom,sc7280-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sc7280-dispcc"; reg = <0 0xaf00000 0 0x20000>;