| Message ID | 1644821755-27059-1-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add APCS support for SDX65 | expand |
On Mon, Feb 14, 2022 at 12:25:55PM +0530, Rohit Agarwal wrote: > In SDX65, the IPC bits are located in the APCS GCC block. Also, this block > can provide clock functionality. Hence, add support for IPC with correct > offset and name of the clock provider. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c > index 9325d2a..3f8612c 100644 > --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c > +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c > @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = { > .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" > }; > > +static const struct qcom_apcs_ipc_data sdx65_apcs_data = { > + .offset = 0x1008, .clk_name = "qcom-sdx65-acps-clk" > +}; > + > static const struct regmap_config apcs_regmap_config = { > .reg_bits = 32, > .reg_stride = 4, > @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { > { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, > { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data }, > { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, > + { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data }, > {} > }; > MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); > -- > 2.7.4 >
On Mon, Feb 14, 2022 at 02:04:14PM +0530, Manivannan Sadhasivam wrote: > On Mon, Feb 14, 2022 at 12:25:55PM +0530, Rohit Agarwal wrote: > > In SDX65, the IPC bits are located in the APCS GCC block. Also, this block > > can provide clock functionality. Hence, add support for IPC with correct > > offset and name of the clock provider. > > > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Thanks, > Mani > > > --- > > drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c > > index 9325d2a..3f8612c 100644 > > --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c > > +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c > > @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = { > > .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" > > }; > > > > +static const struct qcom_apcs_ipc_data sdx65_apcs_data = { > > + .offset = 0x1008, .clk_name = "qcom-sdx65-acps-clk" > > +}; > > + After looking at patch 7/8, I think we should be able to reuse "qcom-sdx55-acps-clk" for SDX65. Thanks, Mani > > static const struct regmap_config apcs_regmap_config = { > > .reg_bits = 32, > > .reg_stride = 4, > > @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { > > { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, > > { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data }, > > { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, > > + { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data }, > > {} > > }; > > MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); > > -- > > 2.7.4 > >
On 2/14/2022 2:19 PM, Manivannan Sadhasivam wrote: > On Mon, Feb 14, 2022 at 02:04:14PM +0530, Manivannan Sadhasivam wrote: >> On Mon, Feb 14, 2022 at 12:25:55PM +0530, Rohit Agarwal wrote: >>> In SDX65, the IPC bits are located in the APCS GCC block. Also, this block >>> can provide clock functionality. Hence, add support for IPC with correct >>> offset and name of the clock provider. >>> >>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> >> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> >> >> Thanks, >> Mani >> >>> --- >>> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ >>> 1 file changed, 5 insertions(+) >>> >>> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c >>> index 9325d2a..3f8612c 100644 >>> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c >>> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c >>> @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = { >>> .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" >>> }; >>> >>> +static const struct qcom_apcs_ipc_data sdx65_apcs_data = { >>> + .offset = 0x1008, .clk_name = "qcom-sdx65-acps-clk" >>> +}; >>> + > After looking at patch 7/8, I think we should be able to reuse > "qcom-sdx55-acps-clk" for SDX65. Yes. Will update the patch. Thanks > > Thanks, > Mani >>> static const struct regmap_config apcs_regmap_config = { >>> .reg_bits = 32, >>> .reg_stride = 4, >>> @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { >>> { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, >>> { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data }, >>> { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, >>> + { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data }, >>> {} >>> }; >>> MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); >>> -- >>> 2.7.4 >>>
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 9325d2a..3f8612c 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = { .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" }; +static const struct qcom_apcs_ipc_data sdx65_apcs_data = { + .offset = 0x1008, .clk_name = "qcom-sdx65-acps-clk" +}; + static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data }, { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, + { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
In SDX65, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ 1 file changed, 5 insertions(+)