From patchwork Mon Feb 14 06:55:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12744999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C6B3C433FE for ; Mon, 14 Feb 2022 06:56:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235577AbiBNG4I (ORCPT ); Mon, 14 Feb 2022 01:56:08 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240948AbiBNG4I (ORCPT ); Mon, 14 Feb 2022 01:56:08 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CF67575C5; Sun, 13 Feb 2022 22:56:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644821761; x=1676357761; h=from:to:cc:subject:date:message-id; bh=jpDeUjRDsp/655wGJHvhHJTwEtScnmkP3LIzmC5nWqQ=; b=yz5HVyPkm6HMHXtXcdpK7s7d1SYFHV0LWj4cnQYXEyvDq7dr5tLCcdl7 cc/ngPqEqNfNp5+2505q48IP4dbYhzNYyC/8D5esldl+F8gTJjct/W1al iKLA3oW9E2ukufTfkVgJeYujFojPWL8p1VB4yaUyO2aJVC4Z+puKK4opG 4=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 13 Feb 2022 22:56:01 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 13 Feb 2022 22:56:00 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 14 Feb 2022 12:25:57 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 2625B4473; Mon, 14 Feb 2022 12:25:57 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 2/8] mailbox: qcom: Add support for SDX65 APCS IPC Date: Mon, 14 Feb 2022 12:25:55 +0530 Message-Id: <1644821755-27059-1-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In SDX65, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 9325d2a..3f8612c 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = { .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" }; +static const struct qcom_apcs_ipc_data sdx65_apcs_data = { + .offset = 0x1008, .clk_name = "qcom-sdx65-acps-clk" +}; + static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data }, { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, + { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);