Message ID | 1644822069-27513-1-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Add APCS support for SDX65 | expand |
On Mon, Feb 14, 2022 at 12:31:09PM +0530, Rohit Agarwal wrote: > On SDX65 there is a separate A7 PLL which is used to provide high > frequency clock to the Cortex A7 CPU via a MUX. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > arch/arm/boot/dts/qcom-sdx65.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index 556a2e3..2900ffe 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -125,6 +125,14 @@ > <0x17802000 0x1000>; > }; > > + a7pll: clock@17808000 { > + compatible = "qcom,sdx65-a7pll"; > + reg = <0x17808000 0x1000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "bi_tcxo"; > + #clock-cells = <0>; > + }; > + > timer@17820000 { > #address-cells = <1>; > #size-cells = <1>; > -- > 2.7.4 >
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 556a2e3..2900ffe 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -125,6 +125,14 @@ <0x17802000 0x1000>; }; + a7pll: clock@17808000 { + compatible = "qcom,sdx65-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>;
On SDX65 there is a separate A7 PLL which is used to provide high frequency clock to the Cortex A7 CPU via a MUX. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- arch/arm/boot/dts/qcom-sdx65.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)