From patchwork Tue Feb 15 10:09:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12746851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09929C433FE for ; Tue, 15 Feb 2022 10:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236315AbiBOKJk (ORCPT ); Tue, 15 Feb 2022 05:09:40 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233726AbiBOKJj (ORCPT ); Tue, 15 Feb 2022 05:09:39 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89A1B88B1D; Tue, 15 Feb 2022 02:09:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644919770; x=1676455770; h=from:to:cc:subject:date:message-id; bh=6AwSMXffc+ZIF68gcqh0h7X3F8Mo1HWIO+7WbtTu0i4=; b=RiIlFbl8L32mEk6Ub85kj8tMvE/5zyiUGuXS3Ighwpl2/DutdLK9r6yN s3l6IIgxbY4G+RaYUqfTsNUHyCnB96WX3i8GE4hbokz+k1Oee40zg60G5 0ZrgfKtAIBs9pouixgBo6/5Q9N1zGqmuAI8Ppd3BwK0PVoZMmZQkH3t6N E=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 15 Feb 2022 02:09:30 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Feb 2022 02:09:28 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 15 Feb 2022 15:39:16 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 2EC904665; Tue, 15 Feb 2022 15:39:16 +0530 (+0530) From: Rohit Agarwal To: manivannan.sadhasivam@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 7/7] clk: qcom: Add SDX65 APCS clock controller support Date: Tue, 15 Feb 2022 15:39:13 +0530 Message-Id: <1644919753-28855-1-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a driver config support for the SDX65 APCS clock controller. It is part of the APCS hardware block, which among other things implements a combined mux and half integer divider functionality. The APCS clock controller has 3 parent clocks: 1. Board XO 2. Fixed rate GPLL0 3. A7 PLL This is required for enabling CPU frequency scaling on SDX65-based platforms. Signed-off-by: Rohit Agarwal --- drivers/clk/qcom/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 10d75d3..05abf78 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -55,13 +55,13 @@ config QCOM_CLK_APCC_MSM8996 drivers for dynamic power management. config QCOM_CLK_APCS_SDX55 - tristate "SDX55 APCS Clock Controller" + tristate "SDX55 and SDX65 APCS Clock Controller" depends on QCOM_APCS_IPC || COMPILE_TEST help - Support for the APCS Clock Controller on SDX55 platform. The + Support for the APCS Clock Controller on SDX55, SDX65 platform. The APCS is managing the mux and divider which feeds the CPUs. Say Y if you want to support CPU frequency scaling on devices - such as SDX55. + such as SDX55, SDX65. config QCOM_CLK_RPM tristate "RPM based Clock Controller"