From patchwork Wed Feb 16 22:05:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 12749117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD3B4C433EF for ; Wed, 16 Feb 2022 22:05:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236433AbiBPWF5 (ORCPT ); Wed, 16 Feb 2022 17:05:57 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:42162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236363AbiBPWF4 (ORCPT ); Wed, 16 Feb 2022 17:05:56 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C61822AED85; Wed, 16 Feb 2022 14:05:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645049144; x=1676585144; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=r7PhsAn0DU0kcg6fQOPFFCydwl9YbcvZh9LyLRaPjgo=; b=Q0MGm60R/j+a6nqI6Cz3ZasJ2zXafaANqPRtpIMbjNeeXDwK4lG9KpRD 3qll7613nxYTLGdtXC0C33SxdDOe+UNa1WXJFMiOof8ja79F4FW20OWJ0 6MlL8ie/H6LFrYT1DNJiqnBApdHa+h9HfvkNjYcAlSiDdbfo7JzZalAfA M=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 16 Feb 2022 14:05:44 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2022 14:05:43 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Wed, 16 Feb 2022 14:05:22 -0800 Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Wed, 16 Feb 2022 14:05:22 -0800 From: Kuogee Hsieh To: , , , , , , , , , CC: Kuogee Hsieh , , , , , , Subject: [PATCH v7 3/4] drm/msm/dpu: replace BIT(x) with correspond marco define string Date: Wed, 16 Feb 2022 14:05:05 -0800 Message-ID: <1645049106-30481-4-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645049106-30481-1-git-send-email-quic_khsieh@quicinc.com> References: <1645049106-30481-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To improve code readability, this patch replace BIT(x) with correspond register bit define string Signed-off-by: Kuogee Hsieh --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index b68e696..8f10aab 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -61,6 +61,12 @@ #define INTF_MUX 0x25C +#define INTF_CFG_ACTIVE_H_EN BIT(29) +#define INTF_CFG_ACTIVE_V_EN BIT(30) + +#define INTF_CFG2_DATABUS_WIDEN BIT(0) +#define INTF_CFG2_DATA_HCTL_EN BIT(4) + static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, const struct dpu_mdss_cfg *m, void __iomem *addr, @@ -139,13 +145,13 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, if (active_h_end) { active_hctl = (active_h_end << 16) | active_h_start; - intf_cfg |= BIT(29); + intf_cfg |= INTF_CFG_ACTIVE_H_EN; } else { active_hctl = 0; } if (active_v_end) - intf_cfg |= BIT(30); + intf_cfg |= INTF_CFG_ACTIVE_V_EN; hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; display_hctl = (hsync_end_x << 16) | hsync_start_x; @@ -156,7 +162,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, * if compression is enabled in 1 pixel per clock mode */ if (p->wide_bus_en) - intf_cfg2 |= (BIT(0) | BIT(4)); + intf_cfg2 |= (INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN); data_width = p->width; @@ -178,8 +184,8 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, active_hctl = (active_h_end << 16) | active_h_start; display_hctl = active_hctl; - intf_cfg |= BIT(29); - intf_cfg |= BIT(30); + intf_cfg |= INTF_CFG_ACTIVE_H_EN; + intf_cfg |= INTF_CFG_ACTIVE_V_EN; } den_polarity = 0;