From patchwork Wed Jun 1 10:45:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12866689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 355A8C433FE for ; Wed, 1 Jun 2022 10:45:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352338AbiFAKpw (ORCPT ); Wed, 1 Jun 2022 06:45:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352273AbiFAKpp (ORCPT ); Wed, 1 Jun 2022 06:45:45 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 121157E1F6; Wed, 1 Jun 2022 03:45:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1654080345; x=1685616345; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=KqNKNoVs5YJHPvnkbtsaNbhLZJ5H/RyC/pZRRxlYdV4=; b=neCKA7FGUz4bCtMLZlt1LLUUyNSQY2mKqS0MRcPhafYop2jJNzxHL0MN fHjJTnQIUDwZaPUtsWpFNvp9Yh8UBUFnG+E4bfm85IAYjQ5zJkwfBruj2 UKtyqMw91FvBOqfW0Osgu3LJKXbRCBSi7SFuLF3pEHzQSYZs2fzzwfHzi k=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 01 Jun 2022 03:45:45 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 01 Jun 2022 03:45:43 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 01 Jun 2022 16:15:20 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 419B23FCD; Wed, 1 Jun 2022 16:15:19 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, manivannan.sadhasivam@linaro.org, Rohit Agarwal Subject: [PATCH 01/11] ARM: dts: qcom: sdx65: Add CPUFreq support Date: Wed, 1 Jun 2022 16:15:02 +0530 Message-Id: <1654080312-5408-2-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1654080312-5408-1-git-send-email-quic_rohiagar@quicinc.com> References: <1654080312-5408-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add CPUFreq support to SDX65 platform using the cpufreq-dt driver. There is no dedicated hardware block available on this platform to carry on the CPUFreq duties. Hence, it is accomplished using the CPU clock and regulators tied together by the operating points table. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index a75e9f1..2530c4f 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -54,6 +54,35 @@ compatible = "arm,cortex-a7"; reg = <0x0>; enable-method = "psci"; + clocks = <&apcs>; + power-domains = <&rpmhpd SDX65_CX_AO>; + power-domain-names = "rpmhpd"; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + required-opps = <&rpmhpd_opp_turbo>; }; };