| Message ID | 1656090912-18074-4-git-send-email-quic_khsieh@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | fix primary corruption issue | expand |
On Fri, 24 Jun 2022 at 20:15, Kuogee Hsieh <quic_khsieh@quicinc.com> wrote: > > The msm_dp_modeset_init() is used to attach DP driver to drm bridge chain. > msm_dp_modeset_init() is executed in the order of index (dp->id) of DP > descriptor table. > > Currently, DP is placed at first entry (dp->id = 0) of descriptor table > and eDP is placed at secondary entry (dp->id = 1 ) of descriptor table. > This means DP will be placed at head of bridge chain and eDP will be > placed right after DP at bridge chain. No, the dp->ids do not have anything to do with the bridge chains. > Drm screen update is happen sequentially in the order from head to tail > of bridge chain. Therefore external DP display will have screen updated > happen before primary eDP display if external DP display presented. > This is wrong screen update order and cause one frame time screen > corruption happen at primary display during external DP plugged in. > > This patch place eDP at first entry (dp->id = 0) of descriptor table and > place DP at secondary entry (dp->id = 1) to have primary eDP locate at > head of bridge chain. This correct screen update order and eliminated > the one frame time screen corruption happen d at primary display. > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > drivers/gpu/drm/msm/dp/dp_display.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c > index a87a9d8..2755ff3 100644 > --- a/drivers/gpu/drm/msm/dp/dp_display.c > +++ b/drivers/gpu/drm/msm/dp/dp_display.c > @@ -143,10 +143,10 @@ static const struct msm_dp_config sc7180_dp_cfg = { > > static const struct msm_dp_config sc7280_dp_cfg = { > .descs = (const struct msm_dp_desc[]) { > - { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, > - .controller_id = MSM_DP_CONTROLLER_0, .wide_bus_en = true }, > { .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP, > .controller_id = MSM_DP_CONTROLLER_1, .wide_bus_en = true }, > + { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, > + .controller_id = MSM_DP_CONTROLLER_0, .wide_bus_en = true }, If the correctness of DP display depends on the order of entries in the dp_desc table, something is terribly wrong in the driver. Please fix that rather than working around it by shuffling the entries in the array. > }, > .num_descs = 2, > }; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index a87a9d8..2755ff3 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -143,10 +143,10 @@ static const struct msm_dp_config sc7180_dp_cfg = { static const struct msm_dp_config sc7280_dp_cfg = { .descs = (const struct msm_dp_desc[]) { - { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, - .controller_id = MSM_DP_CONTROLLER_0, .wide_bus_en = true }, { .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP, .controller_id = MSM_DP_CONTROLLER_1, .wide_bus_en = true }, + { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, + .controller_id = MSM_DP_CONTROLLER_0, .wide_bus_en = true }, }, .num_descs = 2, };
The msm_dp_modeset_init() is used to attach DP driver to drm bridge chain. msm_dp_modeset_init() is executed in the order of index (dp->id) of DP descriptor table. Currently, DP is placed at first entry (dp->id = 0) of descriptor table and eDP is placed at secondary entry (dp->id = 1 ) of descriptor table. This means DP will be placed at head of bridge chain and eDP will be placed right after DP at bridge chain. Drm screen update is happen sequentially in the order from head to tail of bridge chain. Therefore external DP display will have screen updated happen before primary eDP display if external DP display presented. This is wrong screen update order and cause one frame time screen corruption happen at primary display during external DP plugged in. This patch place eDP at first entry (dp->id = 0) of descriptor table and place DP at secondary entry (dp->id = 1) to have primary eDP locate at head of bridge chain. This correct screen update order and eliminated the one frame time screen corruption happen d at primary display. Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> --- drivers/gpu/drm/msm/dp/dp_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)