| Message ID | 1674498274-6010-4-git-send-email-quic_khsieh@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | add display port DSC feature | expand |
On 23/01/2023 20:24, Kuogee Hsieh wrote: > Mainlink_levels determined when two actions to take place by hardware, > a new BS sequence due to start of video and a static HW MVID is sent > to panel. This patch add function to configure mainlink level properly > base on lane number. > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > drivers/gpu/drm/msm/dp/dp_catalog.c | 37 ++++++++++++++++++++++++++++++++++++- > drivers/gpu/drm/msm/dp/dp_catalog.h | 4 +++- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 ++++ > 3 files changed, 43 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c > index 676279d..7ac37d8 100644 > --- a/drivers/gpu/drm/msm/dp/dp_catalog.c > +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c > @@ -1,6 +1,7 @@ > // SPDX-License-Identifier: GPL-2.0-only > /* > - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. > + * Copyright (c) 2017-2023, The Linux Foundation. All rights reserved. > + * Copyright (c) 2021. Qualcomm Innovation Center, Inc. All rights reserved > */ > > #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ > @@ -359,6 +360,40 @@ void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog) > ln_mapping); > } > > +void dp_catalog_ctrl_mainlink_levels(struct dp_catalog *dp_catalog, > + u8 lane_cnt) > +{ > + struct dp_catalog_private *catalog = container_of(dp_catalog, > + struct dp_catalog_private, dp_catalog); > + > + u32 mainlink_levels, safe_to_exit_level = 14; > + > + switch (lane_cnt) { > + case 1: > + safe_to_exit_level = 14; > + break; > + case 2: > + safe_to_exit_level = 8; > + break; > + case 4: > + safe_to_exit_level = 5; > + break; > + default: > + drm_dbg_dp(catalog->drm_dev, "setting the default safe_to_exit_level=%u\n", > + safe_to_exit_level); So, set it here rather than somewhere at the top of the function. > + break; > + } > + > + mainlink_levels = dp_read_link(catalog, REG_DP_MAINLINK_LEVELS); > + mainlink_levels &= 0xFE0; > + mainlink_levels |= safe_to_exit_level; > + > + drm_dbg_dp(catalog->drm_dev, "mainlink_level=0x%x, safe_to_exit_level=0x%x\n", > + mainlink_levels, safe_to_exit_level); > + > + dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels); > +} > + > void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, > bool enable) > { > diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h > index 1f717f4..990c162 100644 > --- a/drivers/gpu/drm/msm/dp/dp_catalog.h > +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h > @@ -1,6 +1,7 @@ > /* SPDX-License-Identifier: GPL-2.0-only */ > /* > - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. > + * Copyright (c) 2017-2023, The Linux Foundation. All rights reserved. > + * Copyright (c) 2021. Qualcomm Innovation Center, Inc. All rights reserved > */ > > #ifndef _DP_CATALOG_H_ > @@ -92,6 +93,7 @@ u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog); > void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state); > void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config); > void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog); > +void dp_catalog_ctrl_mainlink_levels(struct dp_catalog *dp_catalog, u8 lane_cnt); > void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable); > void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb); > void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index dd26ca6..959a78c 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -161,6 +161,8 @@ static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) > u32 cc, tb; > > dp_catalog_ctrl_lane_mapping(ctrl->catalog); > + dp_catalog_ctrl_mainlink_levels(ctrl->catalog, > + ctrl->link->link_params.num_lanes); > dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); > > dp_ctrl_config_ctrl(ctrl); > @@ -1296,6 +1298,8 @@ static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, > { > int ret = 0; > > + dp_catalog_ctrl_mainlink_levels(ctrl->catalog, > + ctrl->link->link_params.num_lanes); > dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); > > if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 676279d..7ac37d8 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2023, The Linux Foundation. All rights reserved. + * Copyright (c) 2021. Qualcomm Innovation Center, Inc. All rights reserved */ #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ @@ -359,6 +360,40 @@ void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog) ln_mapping); } +void dp_catalog_ctrl_mainlink_levels(struct dp_catalog *dp_catalog, + u8 lane_cnt) +{ + struct dp_catalog_private *catalog = container_of(dp_catalog, + struct dp_catalog_private, dp_catalog); + + u32 mainlink_levels, safe_to_exit_level = 14; + + switch (lane_cnt) { + case 1: + safe_to_exit_level = 14; + break; + case 2: + safe_to_exit_level = 8; + break; + case 4: + safe_to_exit_level = 5; + break; + default: + drm_dbg_dp(catalog->drm_dev, "setting the default safe_to_exit_level=%u\n", + safe_to_exit_level); + break; + } + + mainlink_levels = dp_read_link(catalog, REG_DP_MAINLINK_LEVELS); + mainlink_levels &= 0xFE0; + mainlink_levels |= safe_to_exit_level; + + drm_dbg_dp(catalog->drm_dev, "mainlink_level=0x%x, safe_to_exit_level=0x%x\n", + mainlink_levels, safe_to_exit_level); + + dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels); +} + void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable) { diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 1f717f4..990c162 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2023, The Linux Foundation. All rights reserved. + * Copyright (c) 2021. Qualcomm Innovation Center, Inc. All rights reserved */ #ifndef _DP_CATALOG_H_ @@ -92,6 +93,7 @@ u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state); void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config); void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog); +void dp_catalog_ctrl_mainlink_levels(struct dp_catalog *dp_catalog, u8 lane_cnt); void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable); void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb); void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index dd26ca6..959a78c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -161,6 +161,8 @@ static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) u32 cc, tb; dp_catalog_ctrl_lane_mapping(ctrl->catalog); + dp_catalog_ctrl_mainlink_levels(ctrl->catalog, + ctrl->link->link_params.num_lanes); dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); dp_ctrl_config_ctrl(ctrl); @@ -1296,6 +1298,8 @@ static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, { int ret = 0; + dp_catalog_ctrl_mainlink_levels(ctrl->catalog, + ctrl->link->link_params.num_lanes); dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
Mainlink_levels determined when two actions to take place by hardware, a new BS sequence due to start of video and a static HW MVID is sent to panel. This patch add function to configure mainlink level properly base on lane number. Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> --- drivers/gpu/drm/msm/dp/dp_catalog.c | 37 ++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/msm/dp/dp_catalog.h | 4 +++- drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 ++++ 3 files changed, 43 insertions(+), 2 deletions(-)