| Message ID | 1685982557-28326-11-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add devicetree support for SDX75 Modem and IDP | expand |
On 5.06.2023 18:29, Rohit Agarwal wrote: > Add the support of cpufreq to enable the cpufreq scaling > on SDX75 SoC. Also add CPU specific information to build > energy model for EAS. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi > index 47170ae..e1887a4 100644 > --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi > @@ -47,10 +47,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x0>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD0>; > power-domain-names = "psci"; > next-level-cache = <&L2_0>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > L2_0: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -64,10 +68,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x100>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD1>; > power-domain-names = "psci"; > next-level-cache = <&L2_100>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > L2_100: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -78,10 +86,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x200>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD2>; > power-domain-names = "psci"; > next-level-cache = <&L2_200>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > L2_200: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -92,10 +104,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x300>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD3>; > power-domain-names = "psci"; > next-level-cache = <&L2_300>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; That sounds a bit bogus.. Thinking about it, it sounds bogus on most platforms we have support for! I guess SM8250 big cores aren't *really* equally as powerful.. > + dynamic-power-coefficient = <100>; > L2_300: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -605,6 +621,20 @@ > }; > > }; > + > + cpufreq_hw: cpufreq@17d91000 { > + compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss"; > + reg = <0 0x17d91000 0 0x1000>; You used 0x0 instead of 0 everywhere else, please do so here as well to keep things consistent. With that: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > + reg-names = "freq-domain0"; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GPLL0>; > + clock-names = "xo", > + "alternate"; > + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "dcvsh-irq-0"; > + #freq-domain-cells = <1>; > + #clock-cells = <1>; > + }; > }; > > timer {
On Mon, Jun 05, 2023 at 08:21:39PM +0200, Konrad Dybcio wrote: > > > On 5.06.2023 18:29, Rohit Agarwal wrote: > > Add the support of cpufreq to enable the cpufreq scaling > > on SDX75 SoC. Also add CPU specific information to build > > energy model for EAS. > > > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/sdx75.dtsi | 30 ++++++++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi > > index 47170ae..e1887a4 100644 > > --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi > > @@ -47,10 +47,14 @@ > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x0>; > > + clocks = <&cpufreq_hw 0>; > > enable-method = "psci"; > > power-domains = <&CPU_PD0>; > > power-domain-names = "psci"; > > next-level-cache = <&L2_0>; > > + qcom,freq-domain = <&cpufreq_hw 0>; > > + capacity-dmips-mhz = <1024>; > > + dynamic-power-coefficient = <100>; > > L2_0: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -64,10 +68,14 @@ > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x100>; > > + clocks = <&cpufreq_hw 0>; > > enable-method = "psci"; > > power-domains = <&CPU_PD1>; > > power-domain-names = "psci"; > > next-level-cache = <&L2_100>; > > + qcom,freq-domain = <&cpufreq_hw 0>; > > + capacity-dmips-mhz = <1024>; > > + dynamic-power-coefficient = <100>; > > L2_100: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -78,10 +86,14 @@ > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x200>; > > + clocks = <&cpufreq_hw 0>; > > enable-method = "psci"; > > power-domains = <&CPU_PD2>; > > power-domain-names = "psci"; > > next-level-cache = <&L2_200>; > > + qcom,freq-domain = <&cpufreq_hw 0>; > > + capacity-dmips-mhz = <1024>; > > + dynamic-power-coefficient = <100>; > > L2_200: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -92,10 +104,14 @@ > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x300>; > > + clocks = <&cpufreq_hw 0>; > > enable-method = "psci"; > > power-domains = <&CPU_PD3>; > > power-domain-names = "psci"; > > next-level-cache = <&L2_300>; > > + qcom,freq-domain = <&cpufreq_hw 0>; > > + capacity-dmips-mhz = <1024>; > That sounds a bit bogus.. Thinking about it, it sounds bogus on most > platforms we have support for! I guess SM8250 big cores aren't *really* > equally as powerful.. > These are relative values on a given CPU. If a b.L SoC has 2 LITTLE CPUs and 2 big CPUs. The LITTLE CPU capacity is relative to big CPU capacity i.e 1024. Thats the reason for SM8250 having capacity-dmips-mhz as 448 for LITTLE CPUs (0-3) and 1024 as Big CPUs. Since SDx75 has all similar capacity CPUs, setting 1024 or for that matter any value is good enough. Thanks, Pavan
diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 47170ae..e1887a4 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -47,10 +47,14 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD0>; power-domain-names = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -64,10 +68,14 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD1>; power-domain-names = "psci"; next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -78,10 +86,14 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD2>; power-domain-names = "psci"; next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -92,10 +104,14 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD3>; power-domain-names = "psci"; next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -605,6 +621,20 @@ }; }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>; + reg-names = "freq-domain0"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + clock-names = "xo", + "alternate"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; }; timer {
Add the support of cpufreq to enable the cpufreq scaling on SDX75 SoC. Also add CPU specific information to build energy model for EAS. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)