| Message ID | 1693474133-10467-1-git-send-email-quic_varada@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | ccd8ab030643040600a663edde56b434b6f4fb6c |
| Headers | show |
| Series | [v2] clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocks | expand |
On 8/31/2023 2:58 PM, Varadarajan Narayanan wrote: > IPQ5332's GPLL0's nominal/turbo frequency is 800MHz. > This must not be scaled based on the requirement of > dependent clocks. Hence remove the CLK_SET_RATE_PARENT > flag. Reviewed-by: Kathiravan T <quic_kathirav@quicinc.com> > > Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > drivers/clk/qcom/gcc-ipq5332.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c > index b02026f..b836159 100644 > --- a/drivers/clk/qcom/gcc-ipq5332.c > +++ b/drivers/clk/qcom/gcc-ipq5332.c > @@ -71,7 +71,6 @@ static struct clk_fixed_factor gpll0_div2 = { > &gpll0_main.clkr.hw }, > .num_parents = 1, > .ops = &clk_fixed_factor_ops, > - .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -85,7 +84,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { > &gpll0_main.clkr.hw }, > .num_parents = 1, > .ops = &clk_alpha_pll_postdiv_ro_ops, > - .flags = CLK_SET_RATE_PARENT, > }, > }; >
On Thu, 31 Aug 2023 14:58:53 +0530, Varadarajan Narayanan wrote: > IPQ5332's GPLL0's nominal/turbo frequency is 800MHz. > This must not be scaled based on the requirement of > dependent clocks. Hence remove the CLK_SET_RATE_PARENT > flag. > > Applied, thanks! [1/1] clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocks commit: ccd8ab030643040600a663edde56b434b6f4fb6c Best regards,
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index b02026f..b836159 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -71,7 +71,6 @@ static struct clk_fixed_factor gpll0_div2 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -85,7 +84,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, };
IPQ5332's GPLL0's nominal/turbo frequency is 800MHz. This must not be scaled based on the requirement of dependent clocks. Hence remove the CLK_SET_RATE_PARENT flag. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> --- drivers/clk/qcom/gcc-ipq5332.c | 2 -- 1 file changed, 2 deletions(-)