| Message ID | 1694066433-8677-3-git-send-email-quic_krichai@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: qcom: Add support for OPP | expand |
On 7.09.2023 08:00, Krishna chaitanya chundru wrote: > PCIe needs to choose the appropriate performance state of RPMH power > domain based up on the PCIe gen speed. > > So let's add the OPP table support to specify RPMH performance states. > > Use opp-level for the PCIe gen speed for easier use. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > --- [...] > + > + pcie1_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-1 { > + opp-level = <1>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-2 { > + opp-level = <2>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-3 { > + opp-level = <3>; > + required-opps = <&rpmhpd_opp_low_svs>; Is gen3 not supposed to require nom like on pcie0? Also, can all non-maximum OPPs run at just low_svs? Konrad
On 9/7/2023 2:34 PM, Konrad Dybcio wrote: > On 7.09.2023 08:00, Krishna chaitanya chundru wrote: >> PCIe needs to choose the appropriate performance state of RPMH power >> domain based up on the PCIe gen speed. >> >> So let's add the OPP table support to specify RPMH performance states. >> >> Use opp-level for the PCIe gen speed for easier use. >> >> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> --- > [...] > >> + >> + pcie1_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-1 { >> + opp-level = <1>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-2 { >> + opp-level = <2>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-3 { >> + opp-level = <3>; >> + required-opps = <&rpmhpd_opp_low_svs>; > Is gen3 not supposed to require nom like on pcie0? This particular controller instance can operate at low svs for GEN3. > Also, can all non-maximum OPPs run at just low_svs? This depends on the hardware capability, for this instance expect GEN4 remaining can operate in LOW svs. It varies from controller instance to instance and also from target to target. > Konrad - KC
On 7.09.2023 11:56, Krishna Chaitanya Chundru wrote: > > On 9/7/2023 2:34 PM, Konrad Dybcio wrote: >> On 7.09.2023 08:00, Krishna chaitanya chundru wrote: >>> PCIe needs to choose the appropriate performance state of RPMH power >>> domain based up on the PCIe gen speed. >>> >>> So let's add the OPP table support to specify RPMH performance states. >>> >>> Use opp-level for the PCIe gen speed for easier use. >>> >>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >>> --- >> [...] >> >>> + >>> + pcie1_opp_table: opp-table { >>> + compatible = "operating-points-v2"; >>> + >>> + opp-1 { >>> + opp-level = <1>; >>> + required-opps = <&rpmhpd_opp_low_svs>; >>> + }; >>> + >>> + opp-2 { >>> + opp-level = <2>; >>> + required-opps = <&rpmhpd_opp_low_svs>; >>> + }; >>> + >>> + opp-3 { >>> + opp-level = <3>; >>> + required-opps = <&rpmhpd_opp_low_svs>; >> Is gen3 not supposed to require nom like on pcie0? > This particular controller instance can operate at low svs for GEN3. >> Also, can all non-maximum OPPs run at just low_svs? > This depends on the hardware capability, for this instance expect GEN4 remaining can operate in LOW svs. It varies from controller instance to instance and also from target to target. Ok, thanks for confirming Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On Thu, Sep 07, 2023 at 11:30:30AM +0530, Krishna chaitanya chundru wrote: > PCIe needs to choose the appropriate performance state of RPMH power > domain based up on the PCIe gen speed. > > So let's add the OPP table support to specify RPMH performance states. > > Use opp-level for the PCIe gen speed for easier use. > So, you just want to control RPMh performance state using OPP and not clock rates? What will happen if you switch to lowest performance state of RPMh but still run PCIe clocks at max rate? - Mani > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 2a60cf8..a6264a5 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -1820,7 +1820,28 @@ > pinctrl-names = "default"; > pinctrl-0 = <&pcie0_default_state>; > > + operating-points-v2 = <&pcie0_opp_table>; > + > status = "disabled"; > + > + pcie0_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-1 { > + opp-level = <1>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-2 { > + opp-level = <2>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-3 { > + opp-level = <3>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > }; > > pcie0_phy: phy@1c06000 { > @@ -1932,7 +1953,33 @@ > pinctrl-names = "default"; > pinctrl-0 = <&pcie1_default_state>; > > + operating-points-v2 = <&pcie1_opp_table>; > + > status = "disabled"; > + > + pcie1_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-1 { > + opp-level = <1>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-2 { > + opp-level = <2>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-3 { > + opp-level = <3>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-4 { > + opp-level = <4>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > }; > > pcie1_phy: phy@1c0f000 { > -- > 2.7.4 >
On 9/29/2023 12:08 AM, Manivannan Sadhasivam wrote: > On Thu, Sep 07, 2023 at 11:30:30AM +0530, Krishna chaitanya chundru wrote: >> PCIe needs to choose the appropriate performance state of RPMH power >> domain based up on the PCIe gen speed. >> >> So let's add the OPP table support to specify RPMH performance states. >> >> Use opp-level for the PCIe gen speed for easier use. >> > So, you just want to control RPMh performance state using OPP and not clock > rates? What will happen if you switch to lowest performance state of RPMh but > still run PCIe clocks at max rate? > > - Mani Based up on the RPMH state the clock rates will be scaled accordingly. - KC >> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 47 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> index 2a60cf8..a6264a5 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> @@ -1820,7 +1820,28 @@ >> pinctrl-names = "default"; >> pinctrl-0 = <&pcie0_default_state>; >> >> + operating-points-v2 = <&pcie0_opp_table>; >> + >> status = "disabled"; >> + >> + pcie0_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-1 { >> + opp-level = <1>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-2 { >> + opp-level = <2>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-3 { >> + opp-level = <3>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> }; >> >> pcie0_phy: phy@1c06000 { >> @@ -1932,7 +1953,33 @@ >> pinctrl-names = "default"; >> pinctrl-0 = <&pcie1_default_state>; >> >> + operating-points-v2 = <&pcie1_opp_table>; >> + >> status = "disabled"; >> + >> + pcie1_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-1 { >> + opp-level = <1>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-2 { >> + opp-level = <2>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-3 { >> + opp-level = <3>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-4 { >> + opp-level = <4>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> }; >> >> pcie1_phy: phy@1c0f000 { >> -- >> 2.7.4 >>
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 2a60cf8..a6264a5 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1820,7 +1820,28 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + operating-points-v2 = <&pcie0_opp_table>; + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1 { + opp-level = <1>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-2 { + opp-level = <2>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-3 { + opp-level = <3>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; pcie0_phy: phy@1c06000 { @@ -1932,7 +1953,33 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + operating-points-v2 = <&pcie1_opp_table>; + status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1 { + opp-level = <1>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-2 { + opp-level = <2>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-3 { + opp-level = <3>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-4 { + opp-level = <4>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; pcie1_phy: phy@1c0f000 {
PCIe needs to choose the appropriate performance state of RPMH power domain based up on the PCIe gen speed. So let's add the OPP table support to specify RPMH performance states. Use opp-level for the PCIe gen speed for easier use. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+)