From patchwork Thu Jan 16 01:38:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 3496341 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C0417C02DD for ; Thu, 16 Jan 2014 01:39:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E424A2017D for ; Thu, 16 Jan 2014 01:39:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ED06320171 for ; Thu, 16 Jan 2014 01:39:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752147AbaAPBit (ORCPT ); Wed, 15 Jan 2014 20:38:49 -0500 Received: from smtp.codeaurora.org ([198.145.11.231]:49030 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752049AbaAPBim (ORCPT ); Wed, 15 Jan 2014 20:38:42 -0500 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 9C1EC13EF13; Thu, 16 Jan 2014 01:38:41 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 8C04B13F01C; Thu, 16 Jan 2014 01:38:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (i-global252.qualcomm.com [199.106.103.252]) (using SSLv3 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: sboyd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B9DDF13EF13; Thu, 16 Jan 2014 01:38:40 +0000 (UTC) Date: Wed, 15 Jan 2014 17:38:40 -0800 From: Stephen Boyd To: Lorenzo Pieralisi Cc: Borislav Petkov , "linux-kernel@vger.kernel.org" , "linux-arm-msm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-edac@vger.kernel.org" , Mark Rutland , Kumar Gala , "devicetree@vger.kernel.org" Subject: Re: [PATCH v5 2/4] devicetree: bindings: Document Krait CPU/L1 EDAC Message-ID: <20140116013840.GA674@codeaurora.org> References: <1389735034-21430-1-git-send-email-sboyd@codeaurora.org> <1389735034-21430-3-git-send-email-sboyd@codeaurora.org> <20140115102701.GA27314@e102568-lin.cambridge.arm.com> <20140115165623.GJ14405@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20140115165623.GJ14405@codeaurora.org> User-Agent: Mutt/1.5.20 (2009-06-14) X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 01/15, Stephen Boyd wrote: > > Ah sorry, I forgot to put the compatible property here like in > the dts change. I'll do that in the next revision. Yes we need a > compatible property here to match the platform driver. > This is the replacement patch -----8<------ From: Stephen Boyd Subject: [PATCH v9] devicetree: bindings: Document Krait CPU/L1 EDAC The Krait CPU/L1 error reporting device is made up a per-CPU interrupt. While we're here, document the next-level-cache property that's used by the Krait EDAC driver. Cc: Lorenzo Pieralisi Cc: Mark Rutland Cc: Kumar Gala Cc: Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/arm/cpus.txt | 58 ++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 91304353eea4..03a529e791c4 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -62,6 +62,20 @@ nodes to be present and contain the properties described below. Value type: Definition: must be set to 0 + - compatible + Usage: optional + Value type: + Definition: should be one of the compatible strings listed + in the cpu node compatible property. This property + shall only be present if all the cpu nodes have the + same compatible property. + + - interrupts + Usage: required when node contains cpus with compatible + string "qcom,krait". + Value type: + Definition: L1/CPU error interrupt + - cpu node Description: Describes a CPU in an ARM based system @@ -191,6 +205,11 @@ nodes to be present and contain the properties described below. property identifying a 64-bit zero-initialised memory location. + - next-level-cache + Usage: optional + Value type: + Definition: phandle pointing to the next level cache + Example 1 (dual-cluster big.LITTLE system 32-bit): cpus { @@ -382,3 +401,42 @@ cpus { cpu-release-addr = <0 0x20000000>; }; }; + + +Example 5 (Krait 32-bit system): + +cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 9 0xf04>; + compatible = "qcom,krait"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + interrupts = <0 2 0x4>; + }; +};