| Message ID | 20170306080029.3422-1-linus.walleij@linaro.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Andy Gross |
| Headers | show |
On Mon 06 Mar 09:00 CET 2017, Linus Walleij wrote: > To make the picture complete, add DTS entries also for the > second and fourth MMC/SD blocks on the MSM8660. SDC2 is > an 8-bit interface and SDC4 is a 4-bit interface. > > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 03/06, Linus Walleij wrote: > To make the picture complete, add DTS entries also for the > second and fourth MMC/SD blocks on the MSM8660. SDC2 is > an 8-bit interface and SDC4 is a 4-bit interface. > > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > arch/arm/boot/dts/qcom-msm8660.dtsi | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi > index 91c9a62ae725..5564ad131325 100644 > --- a/arch/arm/boot/dts/qcom-msm8660.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi > @@ -392,6 +392,22 @@ > cap-mmc-highspeed; > }; > > + sdcc2: sdcc@12140000 { > + status = "disabled"; > + compatible = "arm,pl18x", "arm,primecell"; > + arm,primecell-periphid = <0x00051180>; > + reg = <0x12140000 0x8000>; > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "cmd_irq"; > + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; > + clock-names = "mclk", "apb_pclk"; > + bus-width = <8>; > + max-frequency = <48000000>; > + non-removable; Should things like non-removable or max-frequency be specified in the base dts? Those seem like board attributes.
On Mon, Mar 6, 2017 at 3:35 PM, Stephen Boyd <sboyd@codeaurora.org> wrote: > On 03/06, Linus Walleij wrote: >> + bus-width = <8>; >> + max-frequency = <48000000>; >> + non-removable; > > Should things like non-removable or max-frequency be specified in > the base dts? Those seem like board attributes. I dropped non-removable, which is obviously a board attribute. max-frequency in this case is a cap on how high the IP can go in this (Qualcomm) variant, on this SoC. A board DTS may need to override it pushing it downwards because of line characteristics. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 91c9a62ae725..5564ad131325 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -392,6 +392,22 @@ cap-mmc-highspeed; }; + sdcc2: sdcc@12140000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12140000 0x8000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + }; + sdcc3: sdcc@12180000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; @@ -408,6 +424,21 @@ no-1-8-v; }; + sdcc4: sdcc@121c0000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x121c0000 0x8000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + }; + sdcc5: sdcc@12200000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>;
To make the picture complete, add DTS entries also for the second and fourth MMC/SD blocks on the MSM8660. SDC2 is an 8-bit interface and SDC4 is a 4-bit interface. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- arch/arm/boot/dts/qcom-msm8660.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)