From patchwork Thu Mar 23 10:28:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 9640729 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 203CE601E9 for ; Thu, 23 Mar 2017 10:29:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 20F9E2847F for ; Thu, 23 Mar 2017 10:29:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 14924284C2; Thu, 23 Mar 2017 10:29:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9D1052847F for ; Thu, 23 Mar 2017 10:29:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932990AbdCWK3W (ORCPT ); Thu, 23 Mar 2017 06:29:22 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56262 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932956AbdCWK3V (ORCPT ); Thu, 23 Mar 2017 06:29:21 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6FF1E60CF1; Thu, 23 Mar 2017 10:29:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1490264955; bh=ry5J5lcaD5vm4j/N80g91xlzS96RpjUWu176hTUciGw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kIgn5zB5RzHyWFpUp1cdIRTH0bJsrmOFNWCgenjZPmS1vxcdnDTFfgb3WrJMvnsrf ExRMhlm7SVlhrRJG6uuAL3DFCgsfk3JZJt1Q1TFId+LMtd4QS+EQrOgiN3aGDutGkT hx2fdlSO1WnLgGCe+XQOwCfJatd/PaYorR54FPE4= Received: from localhost (unknown [202.46.23.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: architt@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2416460E76; Thu, 23 Mar 2017 10:29:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1490264951; bh=ry5J5lcaD5vm4j/N80g91xlzS96RpjUWu176hTUciGw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k4CXMWYdUU+/H1e0YExhVsg4/Y9hOFK4wtx/tgA6IgI2OsLP4G90tcBubBWZ+BNrt /gmep325zh1CMIM4ULgr1cYFLg1ZCQtixjzf0lzjk2BixB7E91Gzkwd+9tY9Dl3oRq uRNKv96aNmVrLAQf3QR/yxCCwv4AlQ0YOEIavfVc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2416460E76 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=architt@codeaurora.org From: Archit Taneja To: robdclark@gmail.com Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Archit Taneja Subject: [PATCH 11/24] drm/msm/mdp5: Add more stuff to CRTC state Date: Thu, 23 Mar 2017 15:58:04 +0530 Message-Id: <20170323102817.15017-12-architt@codeaurora.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170323102817.15017-1-architt@codeaurora.org> References: <20170323102817.15017-1-architt@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Things like vblank/err irq masks, mode of operation (command mode or not) are derivative of the interface and mixer state. Therefore, they need to be a part of the CRTC state too. Add them to mdp5_crtc_state, and assign them in the CRTC's atomic_check() func, so that it can be rolled back to a clean state. Signed-off-by: Archit Taneja --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 19 +++++++++++++++++++ drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 7 +++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index 0f6e545d74ba..c58cf44c058d 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -379,6 +379,7 @@ int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(new_crtc_state); struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; + struct mdp5_interface *intf; bool new_mixer = false; new_mixer = !pipeline->mixer; @@ -394,6 +395,24 @@ int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, mdp5_mixer_release(new_crtc_state->state, old_mixer); } + /* + * these should have been already set up in the encoder's atomic + * check (called by drm_atomic_helper_check_modeset) + */ + intf = pipeline->intf; + + mdp5_cstate->err_irqmask = intf2err(intf->num); + mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf); + + if ((intf->type == INTF_DSI) && + (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) { + mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer); + mdp5_cstate->cmd_mode = true; + } else { + mdp5_cstate->pp_done_irqmask = 0; + mdp5_cstate->cmd_mode = false; + } + return 0; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h index 535848e93f55..c31c193e59f2 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h @@ -132,6 +132,13 @@ struct mdp5_crtc_state { struct mdp5_ctl *ctl; struct mdp5_pipeline pipeline; + + /* these are derivatives of intf/mixer state in mdp5_pipeline */ + u32 vblank_irqmask; + u32 err_irqmask; + u32 pp_done_irqmask; + + bool cmd_mode; }; #define to_mdp5_crtc_state(x) \ container_of(x, struct mdp5_crtc_state, base)