From patchwork Thu Mar 23 10:28:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 9640711 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8214F601E9 for ; Thu, 23 Mar 2017 10:28:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 811BA28438 for ; Thu, 23 Mar 2017 10:28:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 75F50284A5; Thu, 23 Mar 2017 10:28:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0BD9A28438 for ; Thu, 23 Mar 2017 10:28:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754314AbdCWK25 (ORCPT ); Thu, 23 Mar 2017 06:28:57 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55688 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751660AbdCWK25 (ORCPT ); Thu, 23 Mar 2017 06:28:57 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A8E9B60DD1; Thu, 23 Mar 2017 10:28:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1490264935; bh=tmhnzYri2ZSj+XDCIUS77FGCXnxANAQck/uDGwOZLZs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zlki4qweC/kkQSW8J71METp8FuoiycB7F/2dVTjHO//G2fj+5t1nd8H+mwdyyfheo PMG4N3c6AarakllkF/NpwFjGGvIyA92Z3ipGAY6p3MabM6kdGw+zHs1YvDoXqN97rt IF9rvZl6qSik1l4GtdPx8Ow0nCT1UrtvF6srIXXI= Received: from localhost (unknown [202.46.23.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: architt@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id BBBCA60DD1; Thu, 23 Mar 2017 10:28:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1490264933; bh=tmhnzYri2ZSj+XDCIUS77FGCXnxANAQck/uDGwOZLZs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WJQkLr740KJFCA9SFD5/dmselTmG07gCXwdrHjGO+aBM70RDY/G0Jy5NGYi0+KkUY Haflx3trJyXeINuFNwAXf6eFdJ6gVncrrsjzfPhZav5MU+O0VhMqIicpXfIiFS5D+s wJFfdBUBVtNSSBKRAbahT5F1dgyL/Ao8zDdeAdI4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BBBCA60DD1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=architt@codeaurora.org From: Archit Taneja To: robdclark@gmail.com Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Archit Taneja Subject: [PATCH 07/24] drm/msm/mdp5: Remove the pipeline stuff in mdp5_ctl Date: Thu, 23 Mar 2017 15:58:00 +0530 Message-Id: <20170323102817.15017-8-architt@codeaurora.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170323102817.15017-1-architt@codeaurora.org> References: <20170323102817.15017-1-architt@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The mdp5_ctl has an 'op_mode' struct which contains info on the downstream pipeline. Grouping these params together in a struct doesn't serve much purpose in the code. Maybe there was a plan to expand this further that never happened. Remove the op_mode struct, and place its members directly in mdp5_ctl. This will help avoid confusion later when I introduce my own verion of a mdp5 pipeline :) Signed-off-by: Archit Taneja --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 42 +++++++++++++-------------------- 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c index ed184e5491b4..a86f1fd359c3 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c @@ -32,13 +32,6 @@ #define CTL_STAT_BUSY 0x1 #define CTL_STAT_BOOKED 0x2 -struct op_mode { - struct mdp5_interface *intf; - - bool encoder_enabled; - uint32_t start_mask; -}; - struct mdp5_ctl { struct mdp5_ctl_manager *ctlm; @@ -49,7 +42,10 @@ struct mdp5_ctl { u32 status; /* Operation Mode Configuration for the Pipeline */ - struct op_mode pipeline; + struct mdp5_interface *intf; + + bool encoder_enabled; + uint32_t start_mask; /* REG_MDP5_CTL_*() registers access info + lock: */ spinlock_t hw_lock; @@ -181,10 +177,10 @@ int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_interface *intf, struct mdp5_kms *mdp5_kms = get_kms(ctl_mgr); ctl->mixer = mixer; - ctl->pipeline.intf = intf; + ctl->intf = intf; - ctl->pipeline.start_mask = mdp_ctl_flush_mask_lm(mixer->lm) | - mdp_ctl_flush_mask_encoder(intf); + ctl->start_mask = mdp_ctl_flush_mask_lm(mixer->lm) | + mdp_ctl_flush_mask_encoder(intf); /* Virtual interfaces need not set a display intf (e.g.: Writeback) */ if (!mdp5_cfg_intf_is_virtual(intf->type)) @@ -197,16 +193,14 @@ int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_interface *intf, static bool start_signal_needed(struct mdp5_ctl *ctl) { - struct op_mode *pipeline = &ctl->pipeline; - - if (!pipeline->encoder_enabled || pipeline->start_mask != 0) + if (!ctl->encoder_enabled || ctl->start_mask != 0) return false; - switch (pipeline->intf->type) { + switch (ctl->intf->type) { case INTF_WB: return true; case INTF_DSI: - return pipeline->intf->mode == MDP5_INTF_DSI_MODE_COMMAND; + return ctl->intf->mode == MDP5_INTF_DSI_MODE_COMMAND; default: return false; } @@ -230,17 +224,16 @@ static void send_start_signal(struct mdp5_ctl *ctl) static void refill_start_mask(struct mdp5_ctl *ctl) { - struct op_mode *pipeline = &ctl->pipeline; - struct mdp5_interface *intf = pipeline->intf; + struct mdp5_interface *intf = ctl->intf; - pipeline->start_mask = mdp_ctl_flush_mask_lm(ctl->mixer->lm); + ctl->start_mask = mdp_ctl_flush_mask_lm(ctl->mixer->lm); /* * Writeback encoder needs to program & flush * address registers for each page flip.. */ if (intf->type == INTF_WB) - pipeline->start_mask |= mdp_ctl_flush_mask_encoder(intf); + ctl->start_mask |= mdp_ctl_flush_mask_encoder(intf); } /** @@ -256,8 +249,8 @@ int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, bool enabled) if (WARN_ON(!ctl)) return -EINVAL; - ctl->pipeline.encoder_enabled = enabled; - DBG("intf_%d: %s", ctl->pipeline.intf->num, enabled ? "on" : "off"); + ctl->encoder_enabled = enabled; + DBG("intf_%d: %s", ctl->intf->num, enabled ? "on" : "off"); if (start_signal_needed(ctl)) { send_start_signal(ctl); @@ -495,15 +488,14 @@ static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask, u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask) { struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm; - struct op_mode *pipeline = &ctl->pipeline; unsigned long flags; u32 flush_id = ctl->id; u32 curr_ctl_flush_mask; - pipeline->start_mask &= ~flush_mask; + ctl->start_mask &= ~flush_mask; VERB("flush_mask=%x, start_mask=%x, trigger=%x", flush_mask, - pipeline->start_mask, ctl->pending_ctl_trigger); + ctl->start_mask, ctl->pending_ctl_trigger); if (ctl->pending_ctl_trigger & flush_mask) { flush_mask |= MDP5_CTL_FLUSH_CTL;