From patchwork Wed Apr 19 09:13:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 9687107 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8CA4360375 for ; Wed, 19 Apr 2017 09:13:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7E648283E2 for ; Wed, 19 Apr 2017 09:13:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 720D8283F9; Wed, 19 Apr 2017 09:13:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F0B32283E2 for ; Wed, 19 Apr 2017 09:13:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933612AbdDSJN4 (ORCPT ); Wed, 19 Apr 2017 05:13:56 -0400 Received: from mail-lf0-f41.google.com ([209.85.215.41]:32919 "EHLO mail-lf0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761392AbdDSJNt (ORCPT ); Wed, 19 Apr 2017 05:13:49 -0400 Received: by mail-lf0-f41.google.com with SMTP id 88so8965107lfr.0 for ; Wed, 19 Apr 2017 02:13:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GfhPzbe4vib9MtsL77IGpSl2BLNU5TQsi/Ublt1KNG0=; b=NswZj41HjVV6Lwpa9AatXPlxVHH39OSnxhXp1W45FkcFd/X5rjC4rsm02GOIiuHas2 7Fr3K5pPDb9NzFdJBn2KytTLOB/n5a+IQn5zjQZrVh3Y3QfmlEnr/4/eZ75fofeOQ9bW B2AK0hP5AWx2soWFeka3JGwy/CqHO+eD46+b4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GfhPzbe4vib9MtsL77IGpSl2BLNU5TQsi/Ublt1KNG0=; b=IKSk87rDwrI36ylHUR894pq+6PgZiyGwf02kEWD710MxImiVUUjHWAYBQCxE7Yxf8K NjH2XknXoTK8Cv5L1bJhVICvJwV2XyRmXqw1wmmRp+cTsVDJoVwmrqT+d0Qs/DuO/o0j NxPYC1DofBlpNZb1BqcSz3IfIaWEVmuXLr0XthrsmAzYVm3KgTL7OZKMTrMi1v3w9tzh N2vN0217Q1qeJsiRWiymfMLITbxD/4NVEEqS3eT5RTBI+A2IideqhQMj9ComTnZgXI8f xdiwx6j4cKqXKkSOnwy8kQlaV5D1oi/FNNE03wTqBg1O8U3s6IGBxf1Esx/o7kltFr3T fXtg== X-Gm-Message-State: AN3rC/5O0tsDuZsRNO3PIPtcIbHNpABZGl5e4j7+Vip/f9hMARNW/WvT t1bsclkLvW/Ij2ps X-Received: by 10.25.228.209 with SMTP id x78mr586812lfi.145.1492593228296; Wed, 19 Apr 2017 02:13:48 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id q123sm303230ljb.18.2017.04.19.02.13.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Apr 2017 02:13:47 -0700 (PDT) From: Linus Walleij To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 4/5 v2] clk: qcom: Update DT bindings for MSM8660 LCC Date: Wed, 19 Apr 2017 11:13:25 +0200 Message-Id: <20170419091326.11226-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170419091326.11226-1-linus.walleij@linaro.org> References: <20170419091326.11226-1-linus.walleij@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the right compatible string and header for the MSM8660 LCC and some new defines to the dt-bindings header. Take this opportunity to spell out the acronym LPASS for Low-power Audio Subsystem. Cc: devicetree@vger.kernel.org Acked-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Add Rob's ACK. --- .../devicetree/bindings/clock/qcom,lcc.txt | 5 +-- include/dt-bindings/clock/qcom,lcc-msm8660.h | 40 ++++++++++++++++++++++ 2 files changed, 43 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/qcom,lcc-msm8660.h diff --git a/Documentation/devicetree/bindings/clock/qcom,lcc.txt b/Documentation/devicetree/bindings/clock/qcom,lcc.txt index a3c78aa88038..4de51df37f1a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,lcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,lcc.txt @@ -1,10 +1,11 @@ -Qualcomm LPASS Clock & Reset Controller Binding ------------------------------------------------- +Qualcomm Low-power Audio Subsystem (LPASS) Clock & Reset Controller Binding +--------------------------------------------------------------------------- Required properties : - compatible : shall contain only one of the following: "qcom,lcc-msm8960" + "qcom,lcc-msm8660" "qcom,lcc-apq8064" "qcom,lcc-ipq8064" "qcom,lcc-mdm9615" diff --git a/include/dt-bindings/clock/qcom,lcc-msm8660.h b/include/dt-bindings/clock/qcom,lcc-msm8660.h new file mode 100644 index 000000000000..7cddcbd6b1ee --- /dev/null +++ b/include/dt-bindings/clock/qcom,lcc-msm8660.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2017 Linus Walleij + * Qualcomm MSM8660 Low-power Audio Subsystem (LPASS) Clock Controller + * devicetree definitions + */ + +#ifndef _DT_BINDINGS_CLK_LCC_MSM8660_H +#define _DT_BINDINGS_CLK_LCC_MSM8660_H + +#define LPA_PLL0 0 +#define MI2S_OSR_SRC 1 +#define MI2S_OSR_CLK 2 +#define MI2S_DIV_CLK 3 +#define MI2S_BIT_DIV_CLK 4 +#define MI2S_BIT_CLK 5 +#define CODEC_I2S_MIC_OSR_SRC 6 +#define CODEC_I2S_MIC_OSR_CLK 7 +#define CODEC_I2S_MIC_DIV_CLK 8 +#define CODEC_I2S_MIC_BIT_DIV_CLK 9 +#define CODEC_I2S_MIC_BIT_CLK 10 +#define SPARE_I2S_MIC_OSR_SRC 11 +#define SPARE_I2S_MIC_OSR_CLK 12 +#define SPARE_I2S_MIC_DIV_CLK 13 +#define SPARE_I2S_MIC_BIT_DIV_CLK 14 +#define SPARE_I2S_MIC_BIT_CLK 15 +#define CODEC_I2S_SPKR_OSR_SRC 16 +#define CODEC_I2S_SPKR_OSR_CLK 17 +#define CODEC_I2S_SPKR_DIV_CLK 18 +#define CODEC_I2S_SPKR_BIT_DIV_CLK 19 +#define CODEC_I2S_SPKR_BIT_CLK 20 +#define SPARE_I2S_SPKR_OSR_SRC 21 +#define SPARE_I2S_SPKR_OSR_CLK 22 +#define SPARE_I2S_SPKR_DIV_CLK 23 +#define SPARE_I2S_SPKR_BIT_DIV_CLK 24 +#define SPARE_I2S_SPKR_BIT_CLK 25 +#define PCM_SRC 26 +#define PCM_CLK_OUT 27 +#define PCM_CLK 28 + +#endif