From patchwork Wed Jan 17 09:34:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 10168839 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3C16A603ED for ; Wed, 17 Jan 2018 09:35:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B1D0205FD for ; Wed, 17 Jan 2018 09:35:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1E92E22299; Wed, 17 Jan 2018 09:35:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8F987205FD for ; Wed, 17 Jan 2018 09:35:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752324AbeAQJfT (ORCPT ); Wed, 17 Jan 2018 04:35:19 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:45176 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750931AbeAQJfQ (ORCPT ); Wed, 17 Jan 2018 04:35:16 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id EF59A60A08; Wed, 17 Jan 2018 09:35:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516181715; bh=ii2Z94tVLkzjmIsKGTjxuodJZGvHtmMBny3hj2nnLg8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lpcWXSL0i/7GA+qMpOFHVaSJdeXbxsWdJjz+Xmkk4/s3v2Xu2zPo8PyhTJuQlIFAr BeSOa1qGn09kHxLbTX3tj6rPWy4HcHEgF/dnL4JnG7/EurrWZRRSST0VK5S3D7gJpd 7sFRY3aYsU4TWDyU32guarul16lu4P3oEXEw5+RI= Received: from localhost (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: architt@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E5170608BF; Wed, 17 Jan 2018 09:35:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516181713; bh=ii2Z94tVLkzjmIsKGTjxuodJZGvHtmMBny3hj2nnLg8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o40hERahxKh6kluAEf1phcKeoUcf9BJA09eI1P2lrPubVa37LyQUmkREqgjrRW8pm 8EU79ij1Z0/1+w9gb8VccRTUWTF8TeQDInWbm4iLTKBd6oPqckeoULMpTt5jzUJM/3 fQmRnZNawooRuhuIAas0nO9vMH8uenAPPuwTUFZc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E5170608BF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=architt@codeaurora.org From: Archit Taneja To: robdclark@gmail.com Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, latkinso@codeaurora.org, sibis@codeaurora.org, Archit Taneja , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH 6/7] dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY Date: Wed, 17 Jan 2018 15:04:47 +0530 Message-Id: <20180117093448.4102-7-architt@codeaurora.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180117093448.4102-1-architt@codeaurora.org> References: <20180117093448.4102-1-architt@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 9c3ad6bbb9f0..26a1796b7145 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY and PHY - regulator + * "qcom,dsi-phy-14nm" +- reg: Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. - reg-names: The names of register regions. The following regions are required: + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" + For DSI 14nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1). - power-domains: Should be <&mmcc MDSS_GDSC>. @@ -102,6 +109,8 @@ Required properties: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: - vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device node + For 14nm PHY: - vcca-supply: phandle to vcca regulator device node Optional properties: