From patchwork Wed Jan 17 09:34:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 10168841 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D01EC603ED for ; Wed, 17 Jan 2018 09:35:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BB660205FD for ; Wed, 17 Jan 2018 09:35:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AFFD422299; Wed, 17 Jan 2018 09:35:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 54EDC205FD for ; Wed, 17 Jan 2018 09:35:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752184AbeAQJfq (ORCPT ); Wed, 17 Jan 2018 04:35:46 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:45314 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752100AbeAQJfS (ORCPT ); Wed, 17 Jan 2018 04:35:18 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9F01160A37; Wed, 17 Jan 2018 09:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516181717; bh=YkK8u21652NgqZ32hLrL3LaNEabgM04vZCZj4iL7w/k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K62pj9i2e7/UkIWbDE4E+3hoMk/mnj7Fra9/y9RYJ1Lyp0/DmFkjbJDkuTDr3mwSr ZKJxhSGhnmklzMkWQ4gwIxhETPAzkAlkQqEy72EnBAPj6jpeZANfj3sU9V79/FMZTh wayUfQHD6facgwV7Kx3B17JjMgef5YFiPPbJD47E= Received: from localhost (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: architt@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 555BC60A54; Wed, 17 Jan 2018 09:35:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516181717; bh=YkK8u21652NgqZ32hLrL3LaNEabgM04vZCZj4iL7w/k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K62pj9i2e7/UkIWbDE4E+3hoMk/mnj7Fra9/y9RYJ1Lyp0/DmFkjbJDkuTDr3mwSr ZKJxhSGhnmklzMkWQ4gwIxhETPAzkAlkQqEy72EnBAPj6jpeZANfj3sU9V79/FMZTh wayUfQHD6facgwV7Kx3B17JjMgef5YFiPPbJD47E= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 555BC60A54 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=architt@codeaurora.org From: Archit Taneja To: robdclark@gmail.com Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, latkinso@codeaurora.org, sibis@codeaurora.org, Archit Taneja , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH 7/7] dt-bindings: display: msm/dsi: Add updates for SDM845 Date: Wed, 17 Jan 2018 15:04:48 +0530 Message-Id: <20180117093448.4102-8-architt@codeaurora.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180117093448.4102-1-architt@codeaurora.org> References: <20180117093448.4102-1-architt@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SDM845 uses a newer revision (v2.0+) of the 6G DSI controller. This revision has another clock input at the block boundary called the byte interface clock. Specify this new clock in the binding. A 10nm DSI PHY is used along with the controller. Add a compatible string for it and specify its base address/regulator supply needs. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/display/msm/dsi.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 26a1796b7145..518e9cdf0d4b 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -20,6 +20,8 @@ Required properties: * "core" For DSIv2, we need an additional clock: * "src" + For DSI6G v2.0 onwards, we need also need the clock: + * "byte_intf" - assigned-clocks: Parents of "byte" and "pixel" for the given platform. - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. See [1] for details on clock bindings. @@ -87,6 +89,7 @@ Required properties: * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" * "qcom,dsi-phy-14nm" + * "qcom,dsi-phy-10nm" - reg: Physical base address and length of the registers of PLL, PHY. Some revisions require the PHY regulator base address, whereas others require the PHY lane base address. See below for each PHY revision. @@ -95,7 +98,7 @@ Required properties: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" - For DSI 14nm PHY: + For DSI 14nm and 10nm PHYs: * "dsi_pll" * "dsi_phy" * "dsi_phy_lane" @@ -112,6 +115,8 @@ Required properties: - vcca-supply: phandle to vcca regulator device node For 14nm PHY: - vcca-supply: phandle to vcca regulator device node + For 10nm PHY: +- vdds-supply: phandle to vdds regulator device node Optional properties: - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY