From patchwork Mon Oct 15 12:47:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 10641779 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BF1A1157A for ; Mon, 15 Oct 2018 12:48:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ABA4D20182 for ; Mon, 15 Oct 2018 12:48:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C5B52931C; Mon, 15 Oct 2018 12:48:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A66620182 for ; Mon, 15 Oct 2018 12:48:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726590AbeJOUdc (ORCPT ); Mon, 15 Oct 2018 16:33:32 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:39172 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726635AbeJOUdb (ORCPT ); Mon, 15 Oct 2018 16:33:31 -0400 Received: by mail-lj1-f196.google.com with SMTP id p1-v6so17353640ljg.6 for ; Mon, 15 Oct 2018 05:48:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/PR/U/AX2RhoMph28nvtYnU8rTDBHHGBQ0O/iaGYqvc=; b=BMKivcKbI+x0Y4sWpJHyolHUxOS9s69ieyfa99V458mPoNYUMIuroBbEwPbJbmHDg6 8PM68u5UTeeu/idBG7+XcKuk0ePD7PYE/HU+b2w+4OWS2EL1bQ9RhQKz6p8iIa6ImrJu BNTpxn/9m0Qgq+lP8aXALxw3TIdIHLEIN2aZ8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/PR/U/AX2RhoMph28nvtYnU8rTDBHHGBQ0O/iaGYqvc=; b=Z2P7tH7CB2n9PTXeHb6KIzwNxftAgP0fGZYbZFNg1dwmTCeA5qfgoODCi9r16Aiz+O dE28MddnxnGFh0F7BLbje29/cs3qwHyXMFajtsSDFtKgOspmsnbqJm+uCHvR5PLjnFQY lO68LlgLSPC5G0O8pL5V8bblY4VfQQ9fq9C3JCu6xHEKfe50Py+kVNtPq3g0vjl8Mkkv o+mw+SEkQRQZImykR2ohSzk/wzdAfX7jMRKjG6nGv4ImhEes/2eQncsBrh/4JjgmxE3n NkUELQVVbRnwX7OCv+34ED7bTnNR6z69Ts93Wp8LR6TZzRmr/O/Lyy9weS3pKyJxJJk8 slig== X-Gm-Message-State: ABuFfoh7dTjbDpFD6fc/lJPVlwpRsLBn13/UDa3S/KM5zxvRdEKp5+d+ myL2E1wa5HhTaPs8yAMn2S0zFA== X-Google-Smtp-Source: ACcGV63nATLtJnR/+LKQNNBhTAtjx5cN+8M4024GUJXOenZlN6yUfsm0tNlNXF3aXMiw6W1+CaiQjQ== X-Received: by 2002:a2e:8589:: with SMTP id b9-v6mr10900340lji.122.1539607700587; Mon, 15 Oct 2018 05:48:20 -0700 (PDT) Received: from centauri.lan (h-229-118.A785.priv.bahnhof.se. [5.150.229.118]) by smtp.gmail.com with ESMTPSA id h87-v6sm2440966lji.9.2018.10.15.05.48.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Oct 2018 05:48:19 -0700 (PDT) From: Niklas Cassel To: viresh.kumar@linaro.org, sboyd@kernel.org, andy.gross@linaro.org, ulf.hansson@linaro.org, collinsd@codeaurora.org, mka@chromium.org, robh@kernel.org, rnayak@codeaurora.org Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Niklas Cassel Subject: [RFC PATCH] dt-bindings: opp: Extend qcom-opp bindings with properties needed for CPR Date: Mon, 15 Oct 2018 14:47:49 +0200 Message-Id: <20181015124749.27276-1-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20180627045234.27403-3-rnayak@codeaurora.org> References: <20180627045234.27403-3-rnayak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Extend qcom-opp bindings with properties needed for Core Power Reduction (CPR). CPR is included in a great variety of Qualcomm SoC, e.g. msm8916 and msm8996, and was first introduced in msm8974. Signed-off-by: Niklas Cassel --- Hello Rob, Rajendra, Sorry for not replying sooner. Since Rob wanted the binding to be complete before merging, this is my proposal to extend the OPP binding with properties needed to support CPR (both for msm8916 and msm8996). I've discussed the proposal with Viresh, and this proposal seems better than what I previously suggested here: https://lore.kernel.org/lkml/20181005204424.GA29500@centauri.lan/ .../devicetree/bindings/opp/qcom-opp.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/qcom-opp.txt b/Documentation/devicetree/bindings/opp/qcom-opp.txt index db4d970c7ec7..3ab5dd84de86 100644 --- a/Documentation/devicetree/bindings/opp/qcom-opp.txt +++ b/Documentation/devicetree/bindings/opp/qcom-opp.txt @@ -23,3 +23,22 @@ Required properties: representing a corner/level that's communicated with a remote microprocessor (usually called the RPM) which then translates it into a certain voltage on a voltage rail. + +Optional properties: +- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. Even + though a power domain doesn't need a opp-hz, there can be devices in the + power domain that need to know the highest supported frequency for each + corner/level (e.g. CPR), in order to properly initialize the hardware. + +- qcom,fuse-level: A positive value representing the fuse corner/level + associated with this OPP node. Sometimes several corners/levels shares + a certain fuse corner/level. A fuse corner/level contains e.g. ref uV, + min uV, and max uV. + +- qcom,fuse-level-: Named qcom,fuse-level property. This is exactly + similar to the above qcom,fuse-level property, but allows multiple + fuse corners/levels to be provided for the same OPP. At runtime, the + platform can pick a and matching qcom,fuse-level- property + will be enabled for all OPPs. If the platform doesn't pick a specific + or the doesn't match with any qcom,fuse-level- + properties, then qcom,fuse-level property shall be used, if present.