From patchwork Fri Nov 16 18:42:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 10686813 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C09F17DE for ; Fri, 16 Nov 2018 18:43:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0BFD72D79B for ; Fri, 16 Nov 2018 18:43:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EF3F52D804; Fri, 16 Nov 2018 18:43:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 496722D79B for ; Fri, 16 Nov 2018 18:43:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729462AbeKQE4y (ORCPT ); Fri, 16 Nov 2018 23:56:54 -0500 Received: from mail-yb1-f194.google.com ([209.85.219.194]:36876 "EHLO mail-yb1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728039AbeKQE4y (ORCPT ); Fri, 16 Nov 2018 23:56:54 -0500 Received: by mail-yb1-f194.google.com with SMTP id d18-v6so10153940yba.4 for ; Fri, 16 Nov 2018 10:43:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=poorly.run; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VDpPCrArnMouE3356TBR3cuXsC+gQOTJycggwiIBtLE=; b=Mtoxk8tjXfFGzxW7C2C/uJBvpqFqlGn+5oQrYA5Qdd1VL8r+gRcFbaCjt6cs+uqgYT ozU5G4KYk9jWQQgTQnGquIALl88G3r9V3W2NTY2WataaalJG9viA/9PaziAlZZ7GEA3I NHaGVvrw8iUQzZwaZIwsYTpNkTKnc+p5xZKvDwzVFNLS7ltVsgGEYSvvgzqSrya5OCbv Og3dwyBoPwpgB5q5re+V2MNQp4HK7A039JRfs4eZmiyO9LgLPySMlAOnFsqd/SNswlGx 5pIkIW46zZw5g5sxEck98wJRKBH497o1GlOmrTHnTTgry/LklMhWA74w+UmQxWTvJGHZ zOCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VDpPCrArnMouE3356TBR3cuXsC+gQOTJycggwiIBtLE=; b=O4+CBzArtd2pM9RN1zjEHu6l+/bjMDirzWWttB/+5NOYFWdD8ajVGwtUA3B3tIHwLL ZfS1qjpZimDwT+vZ3+GdRuLktcbQNrhCrgMMaxbP6hhnu5nPfM/JLkikf2udwk6Anhw8 azkI0235G0gwhBcKGUq/n24GVZfIhk+zKTWGDHl3jHN2r+FkqtehgsCDLXVqvIuF/Pno PJP/6R23n01jCopB5IDnt41k3QP0L7KqzJr45N+mQZVHzZlqK6EVxbC4CiS+mNQAr3xZ lnQzS3PaAC9J6POqclqZev2MSDtO5CKfe6ZTXv5/I22l0+bDtHjwsIzycFgwjU4ns/1x moeA== X-Gm-Message-State: AGRZ1gJa6yYR/3KyLKRgq6L/bM08AzCcmm9Bti7cBSXrdVJwRSQkglUH fTVkwJsCXE1JVevQjX4On5qMww== X-Google-Smtp-Source: AJdET5dk3wRh1ui/VM8sa7rbe+EIQcnzKrzA8tcZUpExFv1NFOJbT4e+XAM4IGTZ2KUM6+VRQCSWRg== X-Received: by 2002:a5b:b09:: with SMTP id z9-v6mr11055446ybp.483.1542393801229; Fri, 16 Nov 2018 10:43:21 -0800 (PST) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:ad55:b1db:adfe:3b9f]) by smtp.gmail.com with ESMTPSA id b144sm5359134ywa.33.2018.11.16.10.43.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Nov 2018 10:43:20 -0800 (PST) From: Sean Paul To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: robdclark@gmail.com, jsanka@codeaurora.org, Sean Paul Subject: [PATCH v2 08/24] drm/msm: dpu: Move DPU_POWER_HANDLE_DBUS_ID to core_perf Date: Fri, 16 Nov 2018 13:42:18 -0500 Message-Id: <20181116184238.170034-9-sean@poorly.run> X-Mailer: git-send-email 2.19.1.1215.g8438c0b245-goog In-Reply-To: <20181116184238.170034-1-sean@poorly.run> References: <20181116184238.170034-1-sean@poorly.run> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sean Paul It's only used in core_perf, so stick it there (and change the name to reflect that). Changes in v2: - None Reviewed-by: Jeykumar Sankaran Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 34 +++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 17 ++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 +-- .../gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 13 ------- 4 files changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index ef6dd43f8bec..bffc51e496e7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -95,20 +95,20 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, memset(perf, 0, sizeof(struct dpu_core_perf_params)); if (!dpu_cstate->bw_control) { - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { perf->bw_ctl[i] = kms->catalog->perf.max_bw_high * 1000ULL; perf->max_per_pipe_ib[i] = perf->bw_ctl[i]; } perf->core_clk_rate = kms->perf.max_core_clk_rate; } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) { - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { perf->bw_ctl[i] = 0; perf->max_per_pipe_ib[i] = 0; } perf->core_clk_rate = 0; } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) { - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { perf->bw_ctl[i] = kms->perf.fix_core_ab_vote; perf->max_per_pipe_ib[i] = kms->perf.fix_core_ib_vote; } @@ -118,12 +118,12 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, DPU_DEBUG( "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu llcc_ib=%llu llcc_ab=%llu mem_ib=%llu mem_ab=%llu\n", crtc->base.id, perf->core_clk_rate, - perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC], - perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC], - perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC], - perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC], - perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI], - perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI]); + perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_MNOC], + perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MNOC], + perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_LLCC], + perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_LLCC], + perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_EBI], + perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_EBI]); } int dpu_core_perf_crtc_check(struct drm_crtc *crtc, @@ -158,8 +158,8 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, /* obtain new values */ _dpu_core_perf_calc_crtc(kms, crtc, state, &dpu_cstate->new_perf); - for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC; - i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = DPU_CORE_PERF_DATA_BUS_ID_MNOC; + i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl[i]; curr_client_type = dpu_crtc_get_client_type(crtc); @@ -290,7 +290,7 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) if (kms->perf.enable_bw_release) { trace_dpu_cmd_release_bw(crtc->base.id); DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id); - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { dpu_crtc->cur_perf.bw_ctl[i] = 0; _dpu_core_perf_crtc_update_bus(kms, crtc, i); } @@ -367,7 +367,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, new = &dpu_cstate->new_perf; if (_dpu_core_perf_crtc_is_power_on(crtc) && !stop_req) { - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { /* * cases for bus bandwidth update. * 1. new bandwidth vote - "ab or ib vote" is higher @@ -409,13 +409,13 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, update_clk = 1; } trace_dpu_perf_crtc_update(crtc->base.id, - new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC], - new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC], - new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI], + new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MNOC], + new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_LLCC], + new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_EBI], new->core_clk_rate, stop_req, update_bus, update_clk); - for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { if (update_bus & BIT(i)) { ret = _dpu_core_perf_crtc_update_bus(kms, crtc, i); if (ret) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index 68b84d85eb8f..c708451a94a1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -22,6 +22,19 @@ #define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000 +/** + * enum dpu_core_perf_data_bus_id - data bus identifier + * @DPU_CORE_PERF_DATA_BUS_ID_MNOC: DPU/MNOC data bus + * @DPU_CORE_PERF_DATA_BUS_ID_LLCC: MNOC/LLCC data bus + * @DPU_CORE_PERF_DATA_BUS_ID_EBI: LLCC/EBI data bus + */ +enum dpu_core_perf_data_bus_id { + DPU_CORE_PERF_DATA_BUS_ID_MNOC, + DPU_CORE_PERF_DATA_BUS_ID_LLCC, + DPU_CORE_PERF_DATA_BUS_ID_EBI, + DPU_CORE_PERF_DATA_BUS_ID_MAX, +}; + /** * struct dpu_core_perf_params - definition of performance parameters * @max_per_pipe_ib: maximum instantaneous bandwidth request @@ -29,8 +42,8 @@ * @core_clk_rate: core clock rate request */ struct dpu_core_perf_params { - u64 max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MAX]; - u64 bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MAX]; + u64 max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_MAX]; + u64 bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MAX]; u64 core_clk_rate; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index c55cb751e2b4..d8f58caf2772 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1370,8 +1370,8 @@ static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v) seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc)); seq_printf(s, "core_clk_rate: %llu\n", dpu_crtc->cur_perf.core_clk_rate); - for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC; - i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { + for (i = DPU_CORE_PERF_DATA_BUS_ID_MNOC; + i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { seq_printf(s, "bw_ctl[%d]: %llu\n", i, dpu_crtc->cur_perf.bw_ctl[i]); seq_printf(s, "max_per_pipe_ib[%d]: %llu\n", i, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h index 124ebc93c877..7536624c8b20 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h @@ -27,19 +27,6 @@ #define DPU_POWER_EVENT_DISABLE BIT(0) #define DPU_POWER_EVENT_ENABLE BIT(1) -/** - * enum DPU_POWER_HANDLE_DBUS_ID - data bus identifier - * @DPU_POWER_HANDLE_DBUS_ID_MNOC: DPU/MNOC data bus - * @DPU_POWER_HANDLE_DBUS_ID_LLCC: MNOC/LLCC data bus - * @DPU_POWER_HANDLE_DBUS_ID_EBI: LLCC/EBI data bus - */ -enum DPU_POWER_HANDLE_DBUS_ID { - DPU_POWER_HANDLE_DBUS_ID_MNOC, - DPU_POWER_HANDLE_DBUS_ID_LLCC, - DPU_POWER_HANDLE_DBUS_ID_EBI, - DPU_POWER_HANDLE_DBUS_ID_MAX, -}; - /* * struct dpu_power_event - local event registration structure * @client_name: name of the client registering