From patchwork Wed Dec 19 23:55:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10738343 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B03413B5 for ; Wed, 19 Dec 2018 23:56:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 38EE128882 for ; Wed, 19 Dec 2018 23:56:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2BCEA286B0; Wed, 19 Dec 2018 23:56:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C855A286B0 for ; Wed, 19 Dec 2018 23:56:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730121AbeLSXzq (ORCPT ); Wed, 19 Dec 2018 18:55:46 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:46460 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730111AbeLSXzn (ORCPT ); Wed, 19 Dec 2018 18:55:43 -0500 Received: by mail-pl1-f195.google.com with SMTP id t13so10181445ply.13 for ; Wed, 19 Dec 2018 15:55:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6RPkl4pipXk1xl7KCOzzXlRGedEKRmNbPEbbe0d6v+o=; b=cGoeKamKlJDOUz3lBIdjH1lwl/GwvlF6O0AFizYiP8qovoJ9LLdKNfXQIRLOgp7wLn BbD7OIEbGHG1sUbCjJYlOKezVn6TMczEDnIKvJf6/oqVJSQOOriZJy0Q0VGtbUVbIgTi Fa0mbyEUKUGtFEdVbOrn6GLDO4jVu4/ZAejyUgJUYgnw6brEFoHQvQT4PSRCWsTYsssi 1HUn7sVUlHbjqXVSNZtYc31F2Edw50UDzEun0FRFWQTCBOqOHqnmtbTA1jWBV76NaYty KISQ+MtCKxNkVsC/u0Qwr3aSeBEy9vONwW669LK7THx0fDNKH2NmhCDxaGntsCoKViMX AW/w== X-Gm-Message-State: AA+aEWZLgyxgK3pzGKdEzCLO6KIPZeZ7o8s5CSNCykRkYcXQPXB8yftF Ui3D21E0BjVHG4TpZTJuYTZBsxsm1h/aCw== X-Google-Smtp-Source: AFSGD/UKJT1Kky5I7L4k2n7TdBxZMtKEFew7iEcgcE7+cqmttR/md9vFTrG6RsWMbMoYLtmlhf7B+A== X-Received: by 2002:a17:902:108a:: with SMTP id c10mr13392636pla.131.1545263742601; Wed, 19 Dec 2018 15:55:42 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:75a:3f6e:21d:9374]) by smtp.gmail.com with ESMTPSA id t67sm37045048pfd.90.2018.12.19.15.55.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 15:55:41 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , Matthias Kaehlcke , Rob Herring Subject: [PATCH v5 1/8] dt-bindings: msm/dsi: Add ref clock for PHYs Date: Wed, 19 Dec 2018 15:55:21 -0800 Message-Id: <20181219235528.114830-2-mka@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog In-Reply-To: <20181219235528.114830-1-mka@chromium.org> References: <20181219235528.114830-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Allow the PHY drivers to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring --- Changes in v5: - added "Reviewed-by: Rob Herring " tag Changes in v4: - added "Reviewed-by" tags from Stephen and Doug Changes in v3: - added note that the ref clock is only required for new DTS files/entries Changes in v2: - add the ref clock for all PHYs, not only the 10nm one - updated commit message --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd88..9ae9469427207 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -106,6 +106,7 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" (only required for new DTS files/entries) For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: