From patchwork Wed Dec 19 23:55:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10738341 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 420D91399 for ; Wed, 19 Dec 2018 23:56:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2EAC4286B0 for ; Wed, 19 Dec 2018 23:56:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2017928895; Wed, 19 Dec 2018 23:56:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9265A286B0 for ; Wed, 19 Dec 2018 23:56:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730156AbeLSX42 (ORCPT ); Wed, 19 Dec 2018 18:56:28 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:39740 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730153AbeLSXzr (ORCPT ); Wed, 19 Dec 2018 18:55:47 -0500 Received: by mail-pf1-f195.google.com with SMTP id r136so3527777pfc.6 for ; Wed, 19 Dec 2018 15:55:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m6RABKy+RQ632Gx1r+iOUpX5DYoCMTAL7f9pkUnDO08=; b=LFZJU8LNLC1zyIYCByNYUsSo5lfwx4mjhY+0hZL7MM2RbMXFwNWtFIai4hunZ8fqu4 TcAYPqLi1aBF1rb5d/XuvGcyX5cCF1+afxfBTI5XYKV1XQoYCWnD28igOBF+4mrXzU4C ia93UBQah43T9NCKNFAJXyP8lLQP010r+ah3SYi7vuvurztLWOJRpX/Wfadwn0Bd6FP/ 9tGcjF0xMUvHE0TvGcOWW4GDn+AduArtyLucLjVWC3NgO11p2ucUrQGu2LsDjDzW8nbW F5bjKOv4I1clo5S6bnMShvM10ZKWmGq7dlB54NlnLRsS5c4+hYbAYz/ebkGAqDqRjVa9 Eo4g== X-Gm-Message-State: AA+aEWYFiwvDRfXZEFQ1dw+8gAhrasFeE4DntQE4j62S1h6zk6jUmxJ4 /3z0KVOD9bi//Ul5XDoujWlW8ltQDD/Pig== X-Google-Smtp-Source: AFSGD/U7yU7mtMYGDjHOX2SIgraf8zZLQl+pRmkfSvSAfj/zF3zY+r65MK8X0u7O1NgajwaLTjwdSA== X-Received: by 2002:aa7:868f:: with SMTP id d15mr21992413pfo.225.1545263746732; Wed, 19 Dec 2018 15:55:46 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:75a:3f6e:21d:9374]) by smtp.gmail.com with ESMTPSA id t67sm37045048pfd.90.2018.12.19.15.55.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 15:55:45 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , Matthias Kaehlcke Subject: [PATCH v5 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT Date: Wed, 19 Dec 2018 15:55:23 -0800 Message-Id: <20181219235528.114830-4-mka@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog In-Reply-To: <20181219235528.114830-1-mka@chromium.org> References: <20181219235528.114830-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd tag --- Changes in v5: - added missing return keyword in msm_dsi_pll_28nm_init() - added "Reviewed-by: Stephen Boyd " tag Changes in v4: - always use parent rate in dsi_pll_28nm_clk_set_rate() and dsi_pll_28nm_clk_recalc_rate() - pass name of VCO ref clock to pll_28nm_register() instead of storing it in a struct field - updated commit message Changes in v3: - use default name and rate if the ref clock is not specified in the DT - store vco_ref_clk_name instead of vco_ref_clk - dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to unsigned long - fixed check for EPROBE_DEFER - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE Changes in v2: - patch added to the series --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 36 +++++++++++++++------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c index 26e3a01a99c2b..c839464741927 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c @@ -40,7 +40,6 @@ #define NUM_PROVIDED_CLKS 2 -#define VCO_REF_CLK_RATE 19200000 #define VCO_MIN_RATE 350000000 #define VCO_MAX_RATE 750000000 @@ -166,17 +165,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); - rem = rate % VCO_REF_CLK_RATE; + rem = rate % parent_rate; if (rem) { refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; frac_n_mode = 1; - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); + div_fbx1000 = rate / (parent_rate / 500); + gen_vco_clk = div_fbx1000 * (parent_rate / 500); } else { refclk_cfg = 0x0; frac_n_mode = 0; - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); + div_fbx1000 = rate / (parent_rate / 1000); + gen_vco_clk = div_fbx1000 * (parent_rate / 1000); } DBG("refclk_cfg = %d", refclk_cfg); @@ -265,7 +264,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, void __iomem *base = pll_28nm->mmio; u32 sdm0, doubler, sdm_byp_div; u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3; - u32 ref_clk = VCO_REF_CLK_RATE; + u32 ref_clk = parent_rate; unsigned long vco_rate; VERB("parent_rate=%lu", parent_rate); @@ -273,7 +272,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, /* Check to see if the ref clk doubler is enabled */ doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; - ref_clk += (doubler * VCO_REF_CLK_RATE); + ref_clk += (doubler * ref_clk); /* see if it is integer mode or sdm mode */ sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); @@ -514,11 +513,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) pll_28nm->clk_data.clk_num = 0; } -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, + const char *ref_clk_name) { char clk_name[32], parent1[32], parent2[32], vco_name[32]; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_names = &ref_clk_name, .num_parents = 1, .name = vco_name, .flags = CLK_IGNORE_UNUSED, @@ -593,6 +593,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, { struct dsi_pll_28nm *pll_28nm; struct msm_dsi_pll *pll; + struct clk *vco_ref_clk; + const char *vco_ref_clk_name; int ret; if (!pdev) @@ -605,6 +607,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, pll_28nm->pdev = pdev; pll_28nm->id = id; + vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (!IS_ERR(vco_ref_clk)) { + vco_ref_clk_name = __clk_get_name(vco_ref_clk); + } else { + ret = PTR_ERR(vco_ref_clk); + if (ret == -EPROBE_DEFER) + return ERR_PTR(ret); + + dev_warn(&pdev->dev, "'ref' clock is not specified, using default name\n"); + vco_ref_clk_name = "xo"; + } + pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_28nm->mmio)) { dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__); @@ -637,7 +651,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, return ERR_PTR(-EINVAL); } - ret = pll_28nm_register(pll_28nm); + ret = pll_28nm_register(pll_28nm, vco_ref_clk_name); if (ret) { dev_err(&pdev->dev, "failed to register PLL: %d\n", ret); return ERR_PTR(ret);