| Message ID | 20190510043421.31393-8-bjorn.andersson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Qualcomm QCS404 CDSP improvements and fastrpc | expand |
On 09-05-19, 21:34, Bjorn Andersson wrote: > The APPS IOMMU provides contexts for FastRPC, MDP and WLAN, among other > things. Define these. We use the qcom_iommu binding because the ^^^ Double spaces crept in.. > firmware restrictions in incompatible with the arm-smmu. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > arch/arm64/boot/dts/qcom/qcs404.dtsi | 85 ++++++++++++++++++++++++++++ > 1 file changed, 85 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi > index b213f6acad76..fcde4f0334c2 100644 > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi > @@ -378,6 +378,91 @@ > reg = <0x01937000 0x25000>; > }; > > + apps_iommu: iommu@1e20000 { > + compatible = "qcom,qcs404-iommu", "qcom,msm-iommu-v1"; Did we define qcom,qcs404-iommu in bindings, It does not seem to be there in this patch, next or integration one
On Sun 12 May 21:54 PDT 2019, Vinod Koul wrote: > On 09-05-19, 21:34, Bjorn Andersson wrote: > > The APPS IOMMU provides contexts for FastRPC, MDP and WLAN, among other > > things. Define these. We use the qcom_iommu binding because the > ^^^ > Double spaces crept in.. > That's to give you some breathing room while reading it - but not as much as a new paragraph :) > > firmware restrictions in incompatible with the arm-smmu. > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/qcs404.dtsi | 85 ++++++++++++++++++++++++++++ > > 1 file changed, 85 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi > > index b213f6acad76..fcde4f0334c2 100644 > > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi > > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi > > @@ -378,6 +378,91 @@ > > reg = <0x01937000 0x25000>; > > }; > > > > + apps_iommu: iommu@1e20000 { > > + compatible = "qcom,qcs404-iommu", "qcom,msm-iommu-v1"; > > Did we define qcom,qcs404-iommu in bindings, It does not seem to be > there in this patch, next or integration one > No, this was entirely intended to fall back on the generic compatible. That said, further testing of this series indicates that we have a cache issue related to the SMMU. In working out this I came up with a series of patches to the arm-smmu driver that allow us to use this with the standard Qualcomm bootloader. So let's ignore patch 7 and 8 in this series until we know how to deal with the SMMU. Regards, Bjorn
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index b213f6acad76..fcde4f0334c2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -378,6 +378,91 @@ reg = <0x01937000 0x25000>; }; + apps_iommu: iommu@1e20000 { + compatible = "qcom,qcs404-iommu", "qcom,msm-iommu-v1"; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <17>; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + /* Define ranges such that the first bank is at 0x1000 */ + ranges = <0 0x01e20000 0x40000>; + + /* Bank 5: CDSP compute bank 1 */ + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x5000 0x1000>; + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Bank 6: CDSP compute bank 2 */ + iommu-ctx@6000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x6000 0x1000>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Bank 7: CDSP compute bank 3 */ + iommu-ctx@7000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x7000 0x1000>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Bank 8: CDSP compute bank 4 */ + iommu-ctx@8000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x8000 0x1000>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Bank 9: CDSP compute bank 5 */ + iommu-ctx@9000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x9000 0x1000>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Bank 10: MDP */ + iommu-ctx@a000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0xa000 0x1000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Bank 21: WLAN 0 */ + iommu-ctx@15000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x15000 0x1000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Bank 23: ADSP compute bank 2 */ + iommu-ctx@17000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x17000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Bank 24: ADSP compute bank 3 */ + iommu-ctx@18000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x18000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Bank 25: ADSP compute bank 4 */ + iommu-ctx@19000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x19000 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>,
The APPS IOMMU provides contexts for FastRPC, MDP and WLAN, among other things. Define these. We use the qcom_iommu binding because the firmware restrictions in incompatible with the arm-smmu. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 85 ++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+)