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[176.86.136.19]) by smtp.gmail.com with ESMTPSA id i18sm91905591wrp.91.2019.07.31.13.29.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 Jul 2019 13:29:56 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, sboyd@kernel.org, david.brown@linaro.org, jassisinghbrar@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, sibis@codeaurora.org, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net Cc: vkoul@kernel.org, niklas.cassel@linaro.org, georgi.djakov@linaro.org, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, khasim.mohammed@linaro.org Subject: [PATCH v4 12/13] arm64: dts: qcom: qcs404: Add DVFS support Date: Wed, 31 Jul 2019 22:29:28 +0200 Message-Id: <20190731202929.16443-13-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731202929.16443-1-jorge.ramirez-ortiz@linaro.org> References: <20190731202929.16443-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Support dynamic voltage and frequency scaling on qcs404. CPUFreq will soon be superseeded by Core Power Reduction (CPR, a form of Adaptive Voltage Scaling found on some Qualcomm SoCs like the qcs404). Due to the CPR upstreaming already being in progress - and some commits already merged - the following commit will need to be reverted to enable CPUFreq support Author: Jorge Ramirez-Ortiz Date: Thu Jul 25 12:41:36 2019 +0200 cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 5b7d6258e9bf..8cce4a224de2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -36,6 +36,10 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; + }; CPU1: cpu@101 { @@ -46,6 +50,9 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; CPU2: cpu@102 { @@ -56,6 +63,9 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; CPU3: cpu@103 { @@ -66,6 +76,9 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; L2_0: l2-cache { @@ -88,6 +101,24 @@ }; }; + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + opp-microvolt = <1224000 1224000 1224000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <1288000 1288000 1288000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-microvolt = <1384000 1384000 1384000>; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-qcs404", "qcom,scm";