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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a8sm3441912pff.5.2019.10.17.15.19.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 15:19:03 -0700 (PDT) From: Jeffrey Hugo To: agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Jeffrey Hugo Subject: [RFC PATCH 2/4] arm64: dts: qcom: msm8998: Add blsp1_uart3 Date: Thu, 17 Oct 2019 15:18:41 -0700 Message-Id: <20191017221843.8130-3-jeffrey.l.hugo@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191017221843.8130-1-jeffrey.l.hugo@gmail.com> References: <20191017221843.8130-1-jeffrey.l.hugo@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The blsp1_uart3 peripheral appears to be commonly used for interfacing with other SoCs on a platform, such as a wcn3990 to provide bluetooth. Signed-off-by: Jeffrey Hugo --- arch/arm64/boot/dts/qcom/msm8998-pins.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/qcom/msm8998.dtsi | 14 ++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi index 6db70acd38ee..e32d3ab395ea 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi @@ -75,4 +75,17 @@ drive-strength = <2>; /* 2 mA */ }; }; + + blsp1_uart3_on: blsp1_uart3_on { + mux { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "blsp_uart3_a"; + }; + + config { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + drive-strength = <2>; + bias-disable; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index a3465f6bae84..b69a7f38dd36 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1214,6 +1214,20 @@ qcom,num-ees = <4>; }; + blsp1_uart3: serial@c171000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x0c171000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart3_on>; + status = "disabled"; + }; + blsp1_i2c1: i2c@c175000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x0c175000 0x600>;