| Message ID | 20191029164438.17012-3-ulf.hansson@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | cpuidle: psci: Support hierarchical CPU arrangement | expand |
On Tue, Oct 29, 2019 at 05:44:27PM +0100, Ulf Hansson wrote: > Update PSCI DT bindings to allow to represent idle states for CPUs and the > CPU topology, by using a hierarchical layout. Primarily this is done by > re-using the existing DT bindings for PM domains [1] and for PM domain idle > states [2]. > > Let's also add an example into the document for the PSCI DT bindings, to > clearly show the new hierarchical based layout. The currently supported > flattened layout, is already described in the ARM idle states bindings [3], > so let's leave that as is. > > [1] Documentation/devicetree/bindings/power/power_domain.txt > [2] Documentation/devicetree/bindings/power/domain-idle-state.txt > [3] Documentation/devicetree/bindings/arm/idle-states.txt > I thought I had given reviewed by to this. Or may be I confused you giving the big standard example that I want to add here. Anyways, Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> -- Regards, Sudeep
Hi Rob, On Tue, 29 Oct 2019 at 17:44, Ulf Hansson <ulf.hansson@linaro.org> wrote: > > Update PSCI DT bindings to allow to represent idle states for CPUs and the > CPU topology, by using a hierarchical layout. Primarily this is done by > re-using the existing DT bindings for PM domains [1] and for PM domain idle > states [2]. > > Let's also add an example into the document for the PSCI DT bindings, to > clearly show the new hierarchical based layout. The currently supported > flattened layout, is already described in the ARM idle states bindings [3], > so let's leave that as is. > > [1] Documentation/devicetree/bindings/power/power_domain.txt > [2] Documentation/devicetree/bindings/power/domain-idle-state.txt > [3] Documentation/devicetree/bindings/arm/idle-states.txt > > Co-developed-by: Lina Iyer <lina.iyer@linaro.org> > Signed-off-by: Lina Iyer <lina.iyer@linaro.org> > Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> > --- > > Changes in v2: > - Clarifications and also added updates cpus.yaml, to descrive that CPUs > may be attached to PM domains. > > --- > .../devicetree/bindings/arm/cpus.yaml | 15 +++ > .../devicetree/bindings/arm/psci.yaml | 102 ++++++++++++++++++ > 2 files changed, 117 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml > index cb30895e3b67..92a775d6fc0e 100644 > --- a/Documentation/devicetree/bindings/arm/cpus.yaml > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml > @@ -241,6 +241,21 @@ properties: > > where voltage is in V, frequency is in MHz. > > + power-domains: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > + description: > + List of phandles and PM domain specifiers, as defined by bindings of the > + PM domain provider (see also ../power_domain.txt). > + > + power-domain-names: > + $ref: '/schemas/types.yaml#/definitions/string-array' > + description: > + A list of power domain name strings sorted in the same order as the > + power-domains property. > + > + For PSCI based platforms, the name corresponding to the index of the PSCI > + PM domain provider, must be "psci". > + > qcom,saw: > $ref: '/schemas/types.yaml#/definitions/phandle' > description: | > diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml > index 7abdf58b335e..9fed255cc92d 100644 > --- a/Documentation/devicetree/bindings/arm/psci.yaml > +++ b/Documentation/devicetree/bindings/arm/psci.yaml > @@ -102,6 +102,34 @@ properties: > [1] Kernel documentation - ARM idle states bindings > Documentation/devicetree/bindings/arm/idle-states.txt > > + "#power-domain-cells": > + description: > + The number of cells in a PM domain specifier as per binding in [3]. > + Must be 0 as to represent a single PM domain. > + > + ARM systems can have multiple cores, sometimes in an hierarchical > + arrangement. This often, but not always, maps directly to the processor > + power topology of the system. Individual nodes in a topology have their > + own specific power states and can be better represented hierarchically. > + > + For these cases, the definitions of the idle states for the CPUs and the > + CPU topology, must conform to the binding in [3]. The idle states > + themselves must conform to the binding in [4] and must specify the > + arm,psci-suspend-param property. > + > + It should also be noted that, in PSCI firmware v1.0 the OS-Initiated > + (OSI) CPU suspend mode is introduced. Using a hierarchical representation > + helps to implement support for OSI mode and OS implementations may choose > + to mandate it. > + > + [3] Documentation/devicetree/bindings/power/power_domain.txt > + [4] Documentation/devicetree/bindings/power/domain-idle-state.txt > + > + power-domains: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > + description: > + List of phandles and PM domain specifiers, as defined by bindings of the > + PM domain provider. > > required: > - compatible > @@ -160,4 +188,78 @@ examples: > cpu_on = <0x95c10002>; > cpu_off = <0x95c10001>; > }; > + > + - |+ > + > + // Case 4: CPUs and CPU idle states described using the hierarchical model. > + > + cpus { > + I noticed that I got a compiler warning from "make dt_binding_check". I have fixed that by adding the below for the next version. #size-cells = <0>; #address-cells = <1>; Other than that, are you okay with these bindings? Note that, these bindings have been discussed and acked by you earlier. Although since your acked back then, they have been converted to the yaml format, hence why I wanted to double check that I managed to get this right. > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0>; > + enable-method = "psci"; > + power-domains = <&CPU_PD0>; > + power-domain-names = "psci"; > + }; > + > + CPU1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a57", "arm,armv8"; > + reg = <0x100>; > + enable-method = "psci"; > + power-domains = <&CPU_PD1>; > + power-domain-names = "psci"; > + }; > + > + idle-states { > + > + CPU_PWRDN: cpu-power-down { > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0000001>; > + entry-latency-us = <10>; > + exit-latency-us = <10>; > + min-residency-us = <100>; > + }; > + > + CLUSTER_RET: cluster-retention { > + compatible = "domain-idle-state"; > + arm,psci-suspend-param = <0x1000011>; > + entry-latency-us = <500>; > + exit-latency-us = <500>; > + min-residency-us = <2000>; > + }; > + > + CLUSTER_PWRDN: cluster-power-down { > + compatible = "domain-idle-state"; > + arm,psci-suspend-param = <0x1000031>; > + entry-latency-us = <2000>; > + exit-latency-us = <2000>; > + min-residency-us = <6000>; > + }; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + > + CPU_PD0: cpu-pd0 { > + #power-domain-cells = <0>; > + domain-idle-states = <&CPU_PWRDN>; > + power-domains = <&CLUSTER_PD>; > + }; > + > + CPU_PD1: cpu-pd1 { > + #power-domain-cells = <0>; > + domain-idle-states = <&CPU_PWRDN>; > + power-domains = <&CLUSTER_PD>; > + }; > + > + CLUSTER_PD: cluster-pd { > + #power-domain-cells = <0>; > + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; > + }; > + }; > ... > -- > 2.17.1 > Kind regards Uffe
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index cb30895e3b67..92a775d6fc0e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -241,6 +241,21 @@ properties: where voltage is in V, frequency is in MHz. + power-domains: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: + List of phandles and PM domain specifiers, as defined by bindings of the + PM domain provider (see also ../power_domain.txt). + + power-domain-names: + $ref: '/schemas/types.yaml#/definitions/string-array' + description: + A list of power domain name strings sorted in the same order as the + power-domains property. + + For PSCI based platforms, the name corresponding to the index of the PSCI + PM domain provider, must be "psci". + qcom,saw: $ref: '/schemas/types.yaml#/definitions/phandle' description: | diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 7abdf58b335e..9fed255cc92d 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -102,6 +102,34 @@ properties: [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt + "#power-domain-cells": + description: + The number of cells in a PM domain specifier as per binding in [3]. + Must be 0 as to represent a single PM domain. + + ARM systems can have multiple cores, sometimes in an hierarchical + arrangement. This often, but not always, maps directly to the processor + power topology of the system. Individual nodes in a topology have their + own specific power states and can be better represented hierarchically. + + For these cases, the definitions of the idle states for the CPUs and the + CPU topology, must conform to the binding in [3]. The idle states + themselves must conform to the binding in [4] and must specify the + arm,psci-suspend-param property. + + It should also be noted that, in PSCI firmware v1.0 the OS-Initiated + (OSI) CPU suspend mode is introduced. Using a hierarchical representation + helps to implement support for OSI mode and OS implementations may choose + to mandate it. + + [3] Documentation/devicetree/bindings/power/power_domain.txt + [4] Documentation/devicetree/bindings/power/domain-idle-state.txt + + power-domains: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: + List of phandles and PM domain specifiers, as defined by bindings of the + PM domain provider. required: - compatible @@ -160,4 +188,78 @@ examples: cpu_on = <0x95c10002>; cpu_off = <0x95c10001>; }; + + - |+ + + // Case 4: CPUs and CPU idle states described using the hierarchical model. + + cpus { + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + }; + + idle-states { + + CPU_PWRDN: cpu-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: cluster-retention { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000011>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-power-down { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000031>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + }; + }; ...