From patchwork Tue Nov 19 15:46:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 11252369 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 11ACE14C0 for ; Tue, 19 Nov 2019 15:47:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DA6D32230F for ; Tue, 19 Nov 2019 15:47:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="HYmIHL8A" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728365AbfKSPrB (ORCPT ); Tue, 19 Nov 2019 10:47:01 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:43632 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728496AbfKSPqq (ORCPT ); Tue, 19 Nov 2019 10:46:46 -0500 Received: by mail-lj1-f195.google.com with SMTP id y23so23866972ljh.10 for ; Tue, 19 Nov 2019 07:46:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GzXbFQkPrKMVsons+QpYWmVJ2fxp7Rx5snNgvCvieVY=; b=HYmIHL8AbXjecRJqfLytR/mTFMP1mprK77S8qbs6pJZsuxTAoUqfXpSpaGLjyiQU7p Gnar+7Msv8r/T5pz05x4WUPjUmvjBH4jAkrt9IVdKvawzyeFCuLApgbPMfB1NgTTmFYJ cbkMTJeDQpImSBcDupLvseSWAbn6oYK+95bbcG+y1fA3FhwNCatzP8de1Iu1bXCaEKw2 I7BhmhX/SGXXj+eSqQU3VPFzSfHaOPEe+vSzCqxHpn+Xj7+vbxWIlVpBhLQmYFhdVmDZ eWrEFrrO0hE1RH/GP9Lk7nnVp3EmV2wBujQZDhfieV//Qp+ZdJvmPu9IL03vRwX1IEpB 73+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GzXbFQkPrKMVsons+QpYWmVJ2fxp7Rx5snNgvCvieVY=; b=RIFXyI1trFInUA1wNzG5AOw9ySDtSnYvbD7whUfHxSdHNiHRMDze9SzhqP/dLRePr3 OmOqq2IWZVVifiHeazyY0XPsh7dXRc08S/dnZikSblJgAdQFM9qYqV51GmOvqszm2c/H CALwdoF/Ma7LSzzEt8wvPtqzeNvqEKbjM0Yun7BMFzNQ6ZhHc5f97dTq6YTUqGva2YW0 u6NvrtEIr4JrvwqyNhrS94pBK+cPmYS5iEsMs4yRMnolJuWLxkgqXedCtTooPf8bAjCF 1g7FmE2zpE86SJFim9/llzKH/hYHeacMd0+UifviXzYQmKzXzoTj9mT8yX53WHMJCNqM Tlig== X-Gm-Message-State: APjAAAWEAwEc5gE7EoVQshPWYsMa4cXdbgsfqnlDzHOdEUgVTVh2cYuG xlLA0vz6MrG80jIAgYEu0vef8w== X-Google-Smtp-Source: APXvYqxreJXH586CBfoZXHSPYRUvjm/n1g+ta2NaurJx9Ghgg5FeWe2LqFFA1DnvzVSTDHNF0S8t2g== X-Received: by 2002:a2e:3311:: with SMTP id d17mr4592702ljc.237.1574178404108; Tue, 19 Nov 2019 07:46:44 -0800 (PST) Received: from centauri.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id e14sm10128803ljb.75.2019.11.19.07.46.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 07:46:43 -0800 (PST) From: Niklas Cassel To: Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, amit.kucheria@linaro.org, sboyd@kernel.org, vireshk@kernel.org, ulf.hansson@linaro.org, Niklas Cassel , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/5] arm64: dts: qcom: qcs404: Add CPR and populate OPP table Date: Tue, 19 Nov 2019 16:46:18 +0100 Message-Id: <20191119154621.55341-4-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191119154621.55341-1-niklas.cassel@linaro.org> References: <20191119154621.55341-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add CPR and populate OPP table. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 132 +++++++++++++++++++++++++-- 1 file changed, 124 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index d03782e7bc11..30b9c7f8f200 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -44,7 +44,8 @@ #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&pms405_s3>; + power-domains = <&cpr>; + power-domain-names = "cpr"; }; CPU1: cpu@101 { @@ -57,7 +58,8 @@ #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&pms405_s3>; + power-domains = <&cpr>; + power-domain-names = "cpr"; }; CPU2: cpu@102 { @@ -70,7 +72,8 @@ #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&pms405_s3>; + power-domains = <&cpr>; + power-domain-names = "cpr"; }; CPU3: cpu@103 { @@ -83,7 +86,8 @@ #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&pms405_s3>; + power-domains = <&cpr>; + power-domain-names = "cpr"; }; L2_0: l2-cache { @@ -107,20 +111,37 @@ }; cpu_opp_table: cpu-opp-table { - compatible = "operating-points-v2"; + compatible = "operating-points-v2-kryo-cpu"; opp-shared; opp-1094400000 { opp-hz = /bits/ 64 <1094400000>; - opp-microvolt = <1224000 1224000 1224000>; + required-opps = <&cpr_opp1>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; - opp-microvolt = <1288000 1288000 1288000>; + required-opps = <&cpr_opp2>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; - opp-microvolt = <1384000 1384000 1384000>; + required-opps = <&cpr_opp3>; + }; + }; + + cpr_opp_table: cpr-opp-table { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + }; + cpr_opp2: opp2 { + opp-level = <2>; + qcom,opp-fuse-level = <2>; + }; + cpr_opp3: opp3 { + opp-level = <3>; + qcom,opp-fuse-level = <3>; }; }; @@ -310,6 +331,62 @@ tsens_caldata: caldata@d0 { reg = <0x1f8 0x14>; }; + cpr_efuse_speedbin: speedbin@13c { + reg = <0x13c 0x4>; + bits = <2 3>; + }; + cpr_efuse_quot_offset1: qoffset1@231 { + reg = <0x231 0x4>; + bits = <4 7>; + }; + cpr_efuse_quot_offset2: qoffset2@232 { + reg = <0x232 0x4>; + bits = <3 7>; + }; + cpr_efuse_quot_offset3: qoffset3@233 { + reg = <0x233 0x4>; + bits = <2 7>; + }; + cpr_efuse_init_voltage1: ivoltage1@229 { + reg = <0x229 0x4>; + bits = <4 6>; + }; + cpr_efuse_init_voltage2: ivoltage2@22a { + reg = <0x22a 0x4>; + bits = <2 6>; + }; + cpr_efuse_init_voltage3: ivoltage3@22b { + reg = <0x22b 0x4>; + bits = <0 6>; + }; + cpr_efuse_quot1: quot1@22b { + reg = <0x22b 0x4>; + bits = <6 12>; + }; + cpr_efuse_quot2: quot2@22d { + reg = <0x22d 0x4>; + bits = <2 12>; + }; + cpr_efuse_quot3: quot3@230 { + reg = <0x230 0x4>; + bits = <0 12>; + }; + cpr_efuse_ring1: ring1@228 { + reg = <0x228 0x4>; + bits = <0 3>; + }; + cpr_efuse_ring2: ring2@228 { + reg = <0x228 0x4>; + bits = <4 3>; + }; + cpr_efuse_ring3: ring3@229 { + reg = <0x229 0x4>; + bits = <0 3>; + }; + cpr_efuse_revision: revision@218 { + reg = <0x218 0x4>; + bits = <3 3>; + }; }; rng: rng@e3000 { @@ -952,6 +1029,45 @@ clocks = <&sleep_clk>; }; + cpr: power-controller@b018000 { + compatible = "qcom,qcs404-cpr", "qcom,cpr"; + reg = <0x0b018000 0x1000>; + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; + clocks = <&xo_board>; + clock-names = "ref"; + vdd-apc-supply = <&pms405_s3>; + #power-domain-cells = <0>; + operating-points-v2 = <&cpr_opp_table>; + acc-syscon = <&tcsr>; + + nvmem-cells = <&cpr_efuse_quot_offset1>, + <&cpr_efuse_quot_offset2>, + <&cpr_efuse_quot_offset3>, + <&cpr_efuse_init_voltage1>, + <&cpr_efuse_init_voltage2>, + <&cpr_efuse_init_voltage3>, + <&cpr_efuse_quot1>, + <&cpr_efuse_quot2>, + <&cpr_efuse_quot3>, + <&cpr_efuse_ring1>, + <&cpr_efuse_ring2>, + <&cpr_efuse_ring3>, + <&cpr_efuse_revision>; + nvmem-cell-names = "cpr_quotient_offset1", + "cpr_quotient_offset2", + "cpr_quotient_offset3", + "cpr_init_voltage1", + "cpr_init_voltage2", + "cpr_init_voltage3", + "cpr_quotient1", + "cpr_quotient2", + "cpr_quotient3", + "cpr_ring_osc1", + "cpr_ring_osc2", + "cpr_ring_osc3", + "cpr_fuse_revision"; + }; + timer@b120000 { #address-cells = <1>; #size-cells = <1>;