From patchwork Wed Jan 15 14:13:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334887 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6F81314B4 for ; Wed, 15 Jan 2020 14:14:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 441D92467A for ; Wed, 15 Jan 2020 14:14:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="lFG+V7Kb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729146AbgAOOOU (ORCPT ); Wed, 15 Jan 2020 09:14:20 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:46184 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730166AbgAOONY (ORCPT ); Wed, 15 Jan 2020 09:13:24 -0500 Received: by mail-wr1-f65.google.com with SMTP id z7so15841402wrl.13 for ; Wed, 15 Jan 2020 06:13:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9aBaxFgJsTga954Qm6zNhUUnNGmgfW34IhkNOpEshlk=; b=lFG+V7KbRtKUR58h85Ew+6RHQb90bJ/Ow0VU5/XrCz7/XsKIE26cPIT+GGdFDPKVcs OwDoGOou1RfgDYWbvZuxLl+G6zLG+VZbFdPjsKi3y3U2VRYcfRz84gRfrSFe56ijzQtE AO14sb+K/tT0fBVDEouCOpj+Rn5OQDBhFophY7ysM2oaDoT9xGxVhSIP6l26dGVNHmBP QjdGTXYRt50/VGM3AU+zRr5lyif/kACNzHUqgxycisOZ6feU4PK0TC4Ays6iQGztGkGb Je7a2mp+hKulKW0Or0BNmHIVPt2UuUnu6apBjNUxR1oiRgHjx0DxkfBWmY1qyF262HIN db0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9aBaxFgJsTga954Qm6zNhUUnNGmgfW34IhkNOpEshlk=; b=GhFpiPJQYke/uDQAD9a+DUkaJQpS4OEaOYYdFofiioEwaQCDmSlTvBRdkqDcJiesXa QpkHVPVPd/Pl+WQzFWIpkXhJMi37fE3Xm2Bzj6G3+zkJ93ChMhsFoPq98fHq0Lpv1+e8 MvMR/va4MbbHCEqSKTb1S6hgovIpcMe6yrx47E7xFtgHZl+hECY9fD7/yxEe+C0nC/I1 eSsFwWxOsIDqu7DQiR/JPMZqN+oJnCWPCBtYmsALMM1SwY0qHcS9jeC1c7iMvC4biQO+ lVFeUAnZK0VOHmd/E3CU1X6hKY9EsntZztlyN1Mfke63ra1MizS6jR3lMtkAQMhuEUl5 dnAg== X-Gm-Message-State: APjAAAWwSrkVLVt/59U2lZQSiEPryHp0y3RcGmmjgm8rrOiZwQndEMH6 Y9h9p0K9GVae+oYaHmAyMJfPzorq8FM= X-Google-Smtp-Source: APXvYqzNW7YiZWcM34HOLFv0zjGD7SaO1QjCQnXbkcWRwP+zmaniq66baux42mlmJeoD8H3iLCwyxQ== X-Received: by 2002:a5d:6652:: with SMTP id f18mr14714314wrw.246.1579097601858; Wed, 15 Jan 2020 06:13:21 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:21 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Vinod Koul , Shawn Guo , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH 12/19] arm64: dts: qcom: qcs404: Add USB devices and PHYs Date: Wed, 15 Jan 2020 14:13:26 +0000 Message-Id: <20200115141333.1222676-13-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bjorn Andersson QCS404 sports HS and SS USB controllers based on dwc3 block with two HS PHYs and one SS PHY. Add nodes for these devices and enable them for EVB board. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Shawn Guo Cc: Andy Gross Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 100 +++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index f5f0c4c9cb16..73565a5b99d1 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -272,6 +272,48 @@ rpm_msg_ram: memory@60000 { reg = <0x00060000 0x6000>; }; + usb3_phy: phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x00078000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "phy", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + status = "disabled"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x0007a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x0007c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + qfprom: qfprom@a4000 { compatible = "qcom,qfprom"; reg = <0x000a4000 0x1000>; @@ -379,6 +421,64 @@ glink-edge { }; }; + usb3: usb@7678800 { + compatible = "qcom,dwc3"; + reg = <0x07678800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + status = "disabled"; + + dwc3@7580000 { + compatible = "snps,dwc3"; + reg = <0x07580000 0xcd00>; + interrupts = ; + phys = <&usb2_phy_sec>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "otg"; + }; + }; + + usb2: usb@79b8800 { + compatible = "qcom,dwc3"; + reg = <0x079b8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_PCNOC_USB2_CLK>, + <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + status = "disabled"; + + dwc3@78c0000 { + compatible = "snps,dwc3"; + reg = <0x078c0000 0xcc00>; + interrupts = ; + phys = <&usb2_phy_prim>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "peripheral"; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>,