From patchwork Mon Feb 10 21:39:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11374113 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B962B1820 for ; Mon, 10 Feb 2020 21:40:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B30120838 for ; Mon, 10 Feb 2020 21:40:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="m595dQRG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727577AbgBJVkG (ORCPT ); Mon, 10 Feb 2020 16:40:06 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:53549 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727579AbgBJVkF (ORCPT ); Mon, 10 Feb 2020 16:40:05 -0500 Received: by mail-wm1-f68.google.com with SMTP id s10so918303wmh.3 for ; Mon, 10 Feb 2020 13:40:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C1WY7m7LZykVt5uJs3pBqs/4NQKr7Ot6cOn9UjLkSJM=; b=m595dQRGCxQ2u1fqafnlK1isvgOXjuOK0l1YeRCmEj/cI7AepSdtOBx7DD9hML0QkY xBx31A5vdqNkk7kpLz2N+0pqvSSmEomEt6LsZM3N/G+dqzU9xA9+YyjUiCEI+/Q96+hE 163z38xlu4D5R/8ypttpnbU1QbbZdAjBvfFE4HRM0j9queioaJW9pv8OoJAovbbGIVH7 a5WaMiBg2tUsv/CZDBoBI75mPYSFxU3fDtH4KoQQz7B8nXCPkMOt69IvVj7jeWLvXWm7 HTxO8ruYjBPTix13y7P3V26UvoAoOCn3ubhB+dKb7uqMSZLx1h14r66rY/ppD+zqR6CN m9Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C1WY7m7LZykVt5uJs3pBqs/4NQKr7Ot6cOn9UjLkSJM=; b=fKbTQB9hIg37KgKz8SsaZFYygNo1A+a/bNE+Fzr1RlZaboy98Meq+8lR7j8E1KpJvx OSXOTnSyawzvG2UWKwAypn5dFcQzbEso544v7tGazBRaOtoYoHDb5Nrky60IDyluRVnk fPgi02w2xMh7cvC8uGn4xQu3ZSTT/87kalQ0amTJ7DY3e+9Hr3w9gpb4msHKs41SjX3c epyuosSTcXh6LJyrU3mTs3vpnERqUbdTMUw+SpZ2qdiESXsMFFPsqb40bbn1Fb6dJq2E 4E4R1MpDrL5IPkwFcunvXurFtwQNYl026ZDR8GJaMs+TvJTu8qQkTjcja8YFdDN3Y8EQ StVg== X-Gm-Message-State: APjAAAXiPyuF7pdhddsLukcuBpRKjhHKgzTY2/rRd07Hv9lj6+FhIpL0 x8hFjykqIOPqLPK4Q50TChY6gQ== X-Google-Smtp-Source: APXvYqzXmPFVDvYGGO1lCbsNxXyqlxO/kA1C/Zdq1de/H66qIAbSiiNtf3Ha+C06PxLj3o/ajaSvhw== X-Received: by 2002:a1c:67c3:: with SMTP id b186mr1016506wmc.36.1581370802162; Mon, 10 Feb 2020 13:40:02 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:a1cf:b00b:5683:ed40]) by smtp.gmail.com with ESMTPSA id u14sm2118582wrm.51.2020.02.10.13.40.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2020 13:40:01 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, coresight@lists.linaro.org, linux-doc@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, robh+dt@kernel.org, maxime@cerno.tech, liviu.dudau@arm.com, sudeep.holla@arm.com, lorenzo.pieralisi@arm.com, agross@kernel.org, corbet@lwn.net Subject: [PATCH v9 10/15] dt-bindings: qcom: Add CTI options for qcom msm8916 Date: Mon, 10 Feb 2020 21:39:19 +0000 Message-Id: <20200210213924.20037-11-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200210213924.20037-1-mike.leach@linaro.org> References: <20200210213924.20037-1-mike.leach@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds system and CPU bound CTI definitions for Qualcom msm8916 platform (Dragonboard DB410C). System CTIs 2-11 are omitted as no information available at present. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier Acked-by: Suzuki K Poulose --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 85 +++++++++++++++++++++++++-- 1 file changed, 81 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 9f31064f2374..d13b5fb5c4d6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -1409,7 +1410,7 @@ cpu = <&CPU3>; }; - etm@85c000 { + etm0: etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85c000 0x1000>; @@ -1427,7 +1428,7 @@ }; }; - etm@85d000 { + etm1: etm@85d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85d000 0x1000>; @@ -1445,7 +1446,7 @@ }; }; - etm@85e000 { + etm2: etm@85e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85e000 0x1000>; @@ -1463,7 +1464,7 @@ }; }; - etm@85f000 { + etm3: etm@85f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85f000 0x1000>; @@ -1481,6 +1482,82 @@ }; }; + /* System CTIs */ + /* CTI 0 - TMC connections */ + cti@810000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTI 1 - TPIU connections */ + cti@811000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x811000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTIs 2-11 - no information - not instantiated */ + + /* Core CTIs; CTIs 12-15 */ + /* CTI - CPU-0 */ + cti@858000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + arm,cs-dev-assoc = <&etm0>; + + }; + + /* CTI - CPU-1 */ + cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + }; + + /* CTI - CPU-2 */ + cti@85a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85a000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + arm,cs-dev-assoc = <&etm2>; + }; + + /* CTI - CPU-3 */ + cti@85b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85b000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + arm,cs-dev-assoc = <&etm3>; + }; + + venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>;