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[93.39.149.95]) by smtp.googlemail.com with ESMTPSA id s5sm3509507wru.39.2020.02.26.17.11.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2020 17:11:22 -0800 (PST) From: Ansuel Smith Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , "David S. Miller" , Rob Herring , Mark Rutland , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 2/2] dt-bindings: net: Add ipq806x mdio bindings Date: Thu, 27 Feb 2020 02:10:46 +0100 Message-Id: <20200227011050.11106-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200227011050.11106-1-ansuelsmth@gmail.com> References: <20200227011050.11106-1-ansuelsmth@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add documentations for ipq806x mdio driver. Signed-off-by: Ansuel Smith --- Changes in v8: - Fix error in dtb check - Remove not needed reset definition from example - Add include header for ipq806x clocks - Fix wrong License type Changes in v7: - Fix dt_binding_check problem .../bindings/net/qcom,ipq8064-mdio.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml diff --git a/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml new file mode 100644 index 000000000000..4334a415f23c --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,ipq8064-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ipq806x MDIO bus controller + +maintainers: + - Ansuel Smith + +description: + The ipq806x soc have a MDIO dedicated controller that is + used to comunicate with the gmac phy conntected. + Child nodes of this MDIO bus controller node are standard + Ethernet PHY device nodes as described in + Documentation/devicetree/bindings/net/phy.txt + +allOf: + - $ref: "mdio.yaml#" + +properties: + compatible: + items: + - const: qcom,ipq8064-mdio + - const: syscon + + reg: + description: address and length of the register set for the device + + clocks: + description: A reference to the clock supplying the MDIO bus controller + + clock-names: + const: master + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + +examples: + - | + #include + + mdio0: mdio@37000000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,ipq8064-mdio", "syscon"; + reg = <0x37000000 0x200000>; + + clocks = <&gcc GMAC_CORE1_CLK>; + + switch@10 { + compatible = "qca,qca8337"; + /* ... */ + }; + };