| Message ID | 20200227105632.15041-8-sibis@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add OSM L3 Interconnect Provider | expand |
On Thu, Feb 27, 2020 at 2:57 AM Sibi Sankar <sibis@codeaurora.org> wrote: > > Add Operation State Manager (OSM) L3 interconnect provider on SC7180 SoCs. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org>
On 2/27/20 12:56, Sibi Sankar wrote: > Add Operation State Manager (OSM) L3 interconnect provider on SC7180 SoCs. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Acked-by: Georgi Djakov <georgi.djakov@linaro.org> Thanks, Georgi
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3e28f340fa3e6..6997467608107 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/qcom,gcc-sc7180.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> #include <dt-bindings/power/qcom-aoss-qmp.h> @@ -1578,6 +1579,16 @@ apps_bcm_voter: bcm_voter { }; }; + osm_l3: interconnect@18321000 { + compatible = "qcom,sc7180-osm-l3"; + reg = <0 0x18321000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18323000 { compatible = "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
Add Operation State Manager (OSM) L3 interconnect provider on SC7180 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)