diff mbox series

[v2] ipq806x: gcc: Added the enable regs and mask for PRNG

Message ID 20200318131657.345-1-ansuelsmth@gmail.com (mailing list archive)
State Accepted
Commit 1aec193ea41d672d11592714cdda8167eb3b38fc
Headers show
Series [v2] ipq806x: gcc: Added the enable regs and mask for PRNG | expand

Commit Message

Christian Marangi March 18, 2020, 1:16 p.m. UTC 
From: Abhishek Sahu <absahu@codeaurora.org>

Kernel got hanged while reading from /dev/hwrng at the
time of PRNG clock enable

Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global
clock controller (GCC)"

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
v2:
 * Fix wrong authorship

 drivers/clk/qcom/gcc-ipq806x.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Stephen Boyd March 20, 2020, 11:28 p.m. UTC | #1 
Quoting Ansuel Smith (2020-03-18 06:16:56)
> From: Abhishek Sahu <absahu@codeaurora.org>
> 
> Kernel got hanged while reading from /dev/hwrng at the
> time of PRNG clock enable
> 
> Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global
> clock controller (GCC)"
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---

Applied to clk-next
Stephen Boyd March 20, 2020, 11:29 p.m. UTC | #2 
Quoting Ansuel Smith (2020-03-18 06:16:56)
> From: Abhishek Sahu <absahu@codeaurora.org>
> 
> Kernel got hanged while reading from /dev/hwrng at the
> time of PRNG clock enable
> 
> Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global
> clock controller (GCC)"

BTW, this should be on one line. Please fix it next time.

> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index b0eee0903807..a8456e09c44d 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -1224,6 +1224,8 @@  static struct clk_rcg prng_src = {
 		.parent_map = gcc_pxo_pll8_map,
 	},
 	.clkr = {
+		.enable_reg = 0x2e80,
+		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "prng_src",
 			.parent_names = gcc_pxo_pll8,