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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:25 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Sham Muthayyan , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/12] pcie: qcom: Programming the PCIE iATU for IPQ806x Date: Fri, 20 Mar 2020 19:34:51 +0100 Message-Id: <20200320183455.21311-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sham Muthayyan Resolved PCIE EP detection errors caused due to missing iATU programming. Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 78 ++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8009e3117765..e26ba8f63d4f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -77,6 +77,30 @@ #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14) #define PCIE_CAP_LINK1_VAL 0x2FD7F +#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10) + +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818 +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c + +#define PCIE20_PLR_IATU_VIEWPORT 0x900 +#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0) + +#define PCIE20_PLR_IATU_CTRL1 0x904 +#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0) +#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0) + +#define PCIE20_PLR_IATU_CTRL2 0x908 +#define PCIE20_PLR_IATU_ENABLE BIT(31) + +#define PCIE20_PLR_IATU_LBAR 0x90C +#define PCIE20_PLR_IATU_UBAR 0x910 +#define PCIE20_PLR_IATU_LAR 0x914 +#define PCIE20_PLR_IATU_LTAR 0x918 +#define PCIE20_PLR_IATU_UTAR 0x91c + +#define MSM_PCIE_DEV_CFG_ADDR 0x01000000 + #define PCIE20_PARF_Q2A_FLUSH 0x1AC #define PCIE20_MISC_CONTROL_1_REG 0x8BC @@ -251,6 +275,57 @@ static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL); } +static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev) +{ + struct pcie_port *pp = &pcie->pci->pp; + + /* + * program and enable address translation region 0 (device config + * address space); region type config; + * axi config address range to device config address range + */ + writel(PCIE20_PLR_IATU_REGION_OUTBOUND | + PCIE20_PLR_IATU_REGION_INDEX(0), + pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT); + + writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1); + writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2); + writel(pp->cfg0_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR); + writel((pp->cfg0_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR); + writel((pp->cfg0_base + pp->cfg0_size - 1), + pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR); + writel(busdev, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR); + writel(0, pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR); +} + +static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie) +{ + struct pcie_port *pp = &pcie->pci->pp; + + /* + * program and enable address translation region 2 (device resource + * address space); region type memory; + * axi device bar address range to device bar address range + */ + writel(PCIE20_PLR_IATU_REGION_OUTBOUND | + PCIE20_PLR_IATU_REGION_INDEX(2), + pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT); + + writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1); + writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2); + writel(pp->mem_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR); + writel((pp->mem_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR); + writel(pp->mem_base + pp->mem_size - 1, + pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR); + writel(pp->mem_bus_addr, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR); + writel(upper_32_bits(pp->mem_bus_addr), + pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR); + + /* 256B PCIE buffer setting */ + writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); +} + static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; @@ -448,6 +523,9 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) writel(CFG_BRIDGE_SB_INIT, pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); + qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR); + qcom_pcie_prog_viewport_mem2_outbound(pcie); + return 0; err_deassert_ahb: