[v4,11/12] arm64: dts: qcom: sdm845: Add cpu OPP tables

Message ID	20200504202243.5476-12-sibis@codeaurora.org (mailing list archive)
State	Superseded
Headers	show Return-Path: <SRS0=xbb/=6S=vger.kernel.org=linux-arm-msm-owner@kernel.org> MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=KmJabrYL7VJNGGwQpVPgoJIMFM2FGXlZT6NeAtc/hC4=; b=dUXNw0yLeygoc2YNdMIowCYpxP1+5AqjQJNUNH3zz7iuTopvgv8uHcNeFSq90Woava19GjeW BqE0SEXZgQhGwsTJe1zT6oU+Dt31ySMRr9Ikidll0rl9omvMRCbYl4ic6vM76VuzkV+ECFUg OCBz2dxZi49Bo/PedZ4OOe6H7zA= sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 07EC8C3855B; Mon, 4 May 2020 20:25:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 07EC8C3855B From: Sibi Sankar <sibis@codeaurora.org> To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, bjorn.andersson@linaro.org, saravanak@google.com, mka@chromium.org Cc: nm@ti.com, agross@kernel.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, ulf.hansson@linaro.org, lukasz.luba@arm.com, sudeep.holla@arm.com, Sibi Sankar <sibis@codeaurora.org> Subject: [PATCH v4 11/12] arm64: dts: qcom: sdm845: Add cpu OPP tables Date: Tue, 5 May 2020 01:52:42 +0530 Message-Id: <20200504202243.5476-12-sibis@codeaurora.org> In-Reply-To: <20200504202243.5476-1-sibis@codeaurora.org> References: <20200504202243.5476-1-sibis@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk
Series	DDR/L3 Scaling support on SDM845 and SC7180 SoCs \| expand [v4,00/12] DDR/L3 Scaling support on SDM845 and SC7180 SoCs [v4,01/12] arm64: dts: qcom: sdm845: Add SoC compatible to MTP [v4,02/12] cpufreq: blacklist SDM845 in cpufreq-dt-platdev [v4,03/12] cpufreq: blacklist SC7180 in cpufreq-dt-platdev [v4,04/12] OPP: Add and export helper to update voltage [v4,05/12] OPP: Add and export helper to set bandwidth [v4,06/12] cpufreq: qcom: Update the bandwidth levels on frequency change [v4,07/12] OPP: Add and export helper to get icc path count [v4,08/12] cpufreq: qcom: Disable fast switch when scaling ddr/l3 [v4,09/12] dt-bindings: interconnect: Add interconnect-tags bindings [v4,10/12] OPP: Add support for setting interconnect-tags [v4,11/12] arm64: dts: qcom: sdm845: Add cpu OPP tables [v4,12/12] arm64: dts: qcom: sc7180: Add cpu OPP tables

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 71dfdfcf2033f..f457a15a8d2b3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/clock/qcom,lpass-sdm845.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,videocc-sdm845.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sdm845.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> @@ -200,6 +201,10 @@ &LITTLE_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -222,6 +227,10 @@ &LITTLE_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -241,6 +250,10 @@ &LITTLE_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_200>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -260,6 +273,10 @@ &LITTLE_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_300>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -279,6 +296,10 @@ &BIG_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_400>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -298,6 +319,10 @@ &BIG_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_500>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -317,6 +342,10 @@ &BIG_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_600>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -336,6 +365,10 @@ &BIG_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_700>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-tags = <3 0>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -433,6 +466,231 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { }; }; + cpu0_opp_table: cpu0_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 4800000>; + }; + + cpu0_opp2: opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-peak-kBps = <800000 4800000>; + }; + + cpu0_opp3: opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-peak-kBps = <800000 6451200>; + }; + + cpu0_opp4: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <800000 6451200>; + }; + + cpu0_opp5: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <800000 7680000>; + }; + + cpu0_opp6: opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + opp-peak-kBps = <1804000 9216000>; + }; + + cpu0_opp7: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <1804000 9216000>; + }; + + cpu0_opp8: opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <1804000 10444800>; + }; + + cpu0_opp9: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <1804000 11980800>; + }; + + cpu0_opp10: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <1804000 11980800>; + }; + + cpu0_opp11: opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-peak-kBps = <2188000 13516800>; + }; + + cpu0_opp12: opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-peak-kBps = <2188000 15052800>; + }; + + cpu0_opp13: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <2188000 16588800>; + }; + + cpu0_opp14: opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <2188000 18124800>; + }; + + cpu0_opp15: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <2724000 19353600>; + }; + + cpu0_opp16: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <4068000 19353600>; + }; + + cpu0_opp17: opp-1689600000 { + opp-hz = /bits/ 64 <1689600000>; + opp-peak-kBps = <4068000 20889600>; + }; + + cpu0_opp18: opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <4068000 22425600>; + }; + }; + + cpu4_opp_table: cpu4_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp1: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <1200000 9216000>; + }; + + cpu4_opp2: opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <1200000 9216000>; + }; + + cpu4_opp3: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <1200000 9216000>; + }; + + cpu4_opp4: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <3072000 11980800>; + }; + + cpu4_opp5: opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <4068000 11980800>; + }; + + cpu4_opp6: opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <4068000 11980800>; + }; + + cpu4_opp7: opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <4068000 15052800>; + }; + + cpu4_opp8: opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <4068000 15052800>; + }; + + cpu4_opp9: opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <4068000 15052800>; + }; + + cpu4_opp10: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <5184000 15052800>; + }; + + cpu4_opp11: opp-1689600000 { + opp-hz = /bits/ 64 <1689600000>; + opp-peak-kBps = <5184000 19353600>; + }; + + cpu4_opp12: opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <6220000 19353600>; + }; + + cpu4_opp13: opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <6220000 19353600>; + }; + + cpu4_opp14: opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <6220000 19353600>; + }; + + cpu4_opp15: opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-peak-kBps = <7216000 20889600>; + }; + + cpu4_opp16: opp-2092800000 { + opp-hz = /bits/ 64 <2092800000>; + opp-peak-kBps = <7216000 20889600>; + }; + + cpu4_opp17: opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <7216000 20889600>; + }; + + cpu4_opp18: opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <7216000 20889600>; + }; + + cpu4_opp19: opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + opp-peak-kBps = <7216000 20889600>; + }; + + cpu4_opp20: opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <7216000 22425600>; + }; + + cpu4_opp21: opp-2476800000 { + opp-hz = /bits/ 64 <2476800000>; + opp-peak-kBps = <7216000 22425600>; + }; + + cpu4_opp22: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <7216000 22425600>; + }; + + cpu4_opp23: opp-2649600000 { + opp-hz = /bits/ 64 <2649600000>; + opp-peak-kBps = <7216000 22425600>; + }; + + cpu4_opp24: opp-2745600000 { + opp-hz = /bits/ 64 <2745600000>; + opp-peak-kBps = <7216000 23654400>; + }; + + cpu4_opp25: opp-2803200000 { + opp-hz = /bits/ 64 <2803200000>; + opp-peak-kBps = <7216000 23654400>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;

[v4,11/12] arm64: dts: qcom: sdm845: Add cpu OPP tables

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