| Message ID | 20200615205333.20747-2-ansuelsmth@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [RESEND,v7,1/2] phy: qualcomm: add qcom ipq806x dwc usb phy driver | expand |
On 15-06-20, 22:53, Ansuel Smith wrote: > Document dwc3 qcom phy hs and ss phy bindings needed to correctly > inizialize and use usb on ipq806x SoC. Rob ? > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> > --- > v7: > * Drop useless AllOf > v6: > * Add maximum value > v5: > * Fix dt_binding_check error > v4: > * Add qcom to specific bindings > v3: > * Use explicit reg instead of regmap > > .../bindings/phy/qcom,ipq806x-usb-phy-hs.yaml | 55 ++++++++++++++ > .../bindings/phy/qcom,ipq806x-usb-phy-ss.yaml | 73 +++++++++++++++++++ > 2 files changed, 128 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml > new file mode 100644 > index 000000000000..23887ebe08fd > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER > + > +maintainers: > + - Ansuel Smith <ansuelsmth@gmail.com> > + > +description: > + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer > + controllers used in ipq806x. Each DWC3 PHY controller should have its > + own node. > + > +properties: > + compatible: > + const: qcom,ipq806x-usb-phy-hs > + > + "#phy-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 2 > + items: > + - const: ref > + - const: xo > + > +required: > + - compatible > + - "#phy-cells" > + - reg > + - clocks > + - clock-names > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-ipq806x.h> > + > + hs_phy_0: phy@110f8800 { > + compatible = "qcom,ipq806x-usb-phy-hs"; > + reg = <0x110f8800 0x30>; > + clocks = <&gcc USB30_0_UTMI_CLK>; > + clock-names = "ref"; > + #phy-cells = <0>; > + }; > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml > new file mode 100644 > index 000000000000..fa30c24b4405 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml > @@ -0,0 +1,73 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER > + > +maintainers: > + - Ansuel Smith <ansuelsmth@gmail.com> > + > +description: > + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer > + controllers used in ipq806x. Each DWC3 PHY controller should have its > + own node. > + > +properties: > + compatible: > + const: qcom,ipq806x-usb-phy-ss > + > + "#phy-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 2 > + items: > + - const: ref > + - const: xo > + > + qcom,rx-eq: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Override value for rx_eq. > + default: 4 > + maximum: 7 > + > + qcom,tx-deamp-3_5db: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Override value for transmit preemphasis. > + default: 23 > + maximum: 63 > + > + qcom,mpll: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Override value for mpll. > + default: 0 > + maximum: 7 > + > +required: > + - compatible > + - "#phy-cells" > + - reg > + - clocks > + - clock-names > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-ipq806x.h> > + > + ss_phy_0: phy@110f8830 { > + compatible = "qcom,ipq806x-usb-phy-ss"; > + reg = <0x110f8830 0x30>; > + clocks = <&gcc USB30_0_MASTER_CLK>; > + clock-names = "ref"; > + #phy-cells = <0>; > + }; > -- > 2.25.1
On Mon, 15 Jun 2020 22:53:27 +0200, Ansuel Smith wrote: > Document dwc3 qcom phy hs and ss phy bindings needed to correctly > inizialize and use usb on ipq806x SoC. > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> > --- > v7: > * Drop useless AllOf > v6: > * Add maximum value > v5: > * Fix dt_binding_check error > v4: > * Add qcom to specific bindings > v3: > * Use explicit reg instead of regmap > > .../bindings/phy/qcom,ipq806x-usb-phy-hs.yaml | 55 ++++++++++++++ > .../bindings/phy/qcom,ipq806x-usb-phy-ss.yaml | 73 +++++++++++++++++++ > 2 files changed, 128 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml new file mode 100644 index 000000000000..23887ebe08fd --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER + +maintainers: + - Ansuel Smith <ansuelsmth@gmail.com> + +description: + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer + controllers used in ipq806x. Each DWC3 PHY controller should have its + own node. + +properties: + compatible: + const: qcom,ipq806x-usb-phy-hs + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: ref + - const: xo + +required: + - compatible + - "#phy-cells" + - reg + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq806x.h> + + hs_phy_0: phy@110f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml new file mode 100644 index 000000000000..fa30c24b4405 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER + +maintainers: + - Ansuel Smith <ansuelsmth@gmail.com> + +description: + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer + controllers used in ipq806x. Each DWC3 PHY controller should have its + own node. + +properties: + compatible: + const: qcom,ipq806x-usb-phy-ss + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: ref + - const: xo + + qcom,rx-eq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Override value for rx_eq. + default: 4 + maximum: 7 + + qcom,tx-deamp-3_5db: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Override value for transmit preemphasis. + default: 23 + maximum: 63 + + qcom,mpll: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Override value for mpll. + default: 0 + maximum: 7 + +required: + - compatible + - "#phy-cells" + - reg + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq806x.h> + + ss_phy_0: phy@110f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x110f8830 0x30>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + };
Document dwc3 qcom phy hs and ss phy bindings needed to correctly inizialize and use usb on ipq806x SoC. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> --- v7: * Drop useless AllOf v6: * Add maximum value v5: * Fix dt_binding_check error v4: * Add qcom to specific bindings v3: * Use explicit reg instead of regmap .../bindings/phy/qcom,ipq806x-usb-phy-hs.yaml | 55 ++++++++++++++ .../bindings/phy/qcom,ipq806x-usb-phy-ss.yaml | 73 +++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml