| Message ID | 20200622222747.717306-6-bjorn.andersson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: qcom: Enable SM8250 remoteprocs | expand |
On Mon, Jun 22, 2020 at 03:27:46PM -0700, Bjorn Andersson wrote: > Add remoteproc nodes for the audio, compute and sensor cores, define > glink for each one and enable them on the MTP with appropriate firmware > defined. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 15 +++ > arch/arm64/boot/dts/qcom/sm8250.dtsi | 116 ++++++++++++++++++++++++ > 2 files changed, 131 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts > index 63d259931c4d..6894f8490dae 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts > +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts > @@ -55,6 +55,11 @@ vreg_s6c_0p88: smpc6-regulator { > }; > }; > > +&adsp { > + status = "okay"; > + firmware-name = "qcom/sm8250/adsp.mbn"; > +}; > + > &apps_rsc { > pm8150-rpmh-regulators { > compatible = "qcom,pm8150-rpmh-regulators"; > @@ -348,10 +353,20 @@ vreg_l7f_1p8: ldo7 { > }; > }; > > +&cdsp { > + status = "okay"; > + firmware-name = "qcom/sm8250/cdsp.mbn"; > +}; > + > &qupv3_id_1 { > status = "okay"; > }; > > +&slpi { > + status = "okay"; > + firmware-name = "qcom/sm8250/slpi.mbn"; > +}; > + > &tlmm { > gpio-reserved-ranges = <28 4>, <40 4>; > }; > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index 364d9a798673..a21299b9c62f 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -1052,6 +1052,83 @@ tcsr_mutex_regs: syscon@1f40000 { > reg = <0x0 0x01f40000 0x0 0x40000>; > }; > > + slpi: remoteproc@5c00000 { > + compatible = "qcom,sm8250-slpi-pas"; > + reg = <0 0x05c00000 0 0x4000>; > + > + interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, > + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", "fatal", "ready", > + "handover", "stop-ack"; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "xo"; > + > + power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, > + <&rpmhpd SM8250_LCX>, > + <&rpmhpd SM8250_LMX>; > + power-domain-names = "load_state", "lcx", "lmx"; > + > + memory-region = <&slpi_mem>; > + > + qcom,smem-states = <&smp2p_slpi_out 0>; > + qcom,smem-state-names = "stop"; > + > + status = "disabled"; > + > + glink-edge { > + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI > + IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + mboxes = <&ipcc IPCC_CLIENT_SLPI > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + label = "lpass"; > + qcom,remote-pid = <3>; > + }; > + }; > + > + cdsp: remoteproc@8300000 { > + compatible = "qcom,sm8250-cdsp-pas"; > + reg = <0 0x08300000 0 0x10000>; > + > + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, > + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", "fatal", "ready", > + "handover", "stop-ack"; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "xo"; > + > + power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, > + <&rpmhpd SM8250_CX>; > + power-domain-names = "load_state", "cx"; > + > + memory-region = <&cdsp_mem>; > + > + qcom,smem-states = <&smp2p_cdsp_out 0>; > + qcom,smem-state-names = "stop"; > + > + status = "disabled"; > + > + glink-edge { > + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP > + IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + mboxes = <&ipcc IPCC_CLIENT_CDSP > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + label = "lpass"; > + qcom,remote-pid = <5>; > + }; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sm8250-pdc", "qcom,pdc"; > reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; > @@ -1668,6 +1745,45 @@ config { > }; > }; > > + adsp: remoteproc@17300000 { > + compatible = "qcom,sm8250-adsp-pas"; > + reg = <0 0x17300000 0 0x100>; > + > + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, > + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", "fatal", "ready", > + "handover", "stop-ack"; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "xo"; > + > + power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, > + <&rpmhpd SM8250_LCX>, > + <&rpmhpd SM8250_LMX>; > + power-domain-names = "load_state", "lcx", "lmx"; > + > + memory-region = <&adsp_mem>; > + > + qcom,smem-states = <&smp2p_adsp_out 0>; > + qcom,smem-state-names = "stop"; > + > + status = "disabled"; > + > + glink-edge { > + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS > + IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + mboxes = <&ipcc IPCC_CLIENT_LPASS > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + label = "lpass"; > + qcom,remote-pid = <2>; > + }; > + }; > + > intc: interrupt-controller@17a00000 { > compatible = "arm,gic-v3"; > #interrupt-cells = <3>; > -- > 2.26.2 >
diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 63d259931c4d..6894f8490dae 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -55,6 +55,11 @@ vreg_s6c_0p88: smpc6-regulator { }; }; +&adsp { + status = "okay"; + firmware-name = "qcom/sm8250/adsp.mbn"; +}; + &apps_rsc { pm8150-rpmh-regulators { compatible = "qcom,pm8150-rpmh-regulators"; @@ -348,10 +353,20 @@ vreg_l7f_1p8: ldo7 { }; }; +&cdsp { + status = "okay"; + firmware-name = "qcom/sm8250/cdsp.mbn"; +}; + &qupv3_id_1 { status = "okay"; }; +&slpi { + status = "okay"; + firmware-name = "qcom/sm8250/slpi.mbn"; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <40 4>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 364d9a798673..a21299b9c62f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1052,6 +1052,83 @@ tcsr_mutex_regs: syscon@1f40000 { reg = <0x0 0x01f40000 0x0 0x40000>; }; + slpi: remoteproc@5c00000 { + compatible = "qcom,sm8250-slpi-pas"; + reg = <0 0x05c00000 0 0x4000>; + + interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, + <&rpmhpd SM8250_LCX>, + <&rpmhpd SM8250_LMX>; + power-domain-names = "load_state", "lcx", "lmx"; + + memory-region = <&slpi_mem>; + + qcom,smem-states = <&smp2p_slpi_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <3>; + }; + }; + + cdsp: remoteproc@8300000 { + compatible = "qcom,sm8250-cdsp-pas"; + reg = <0 0x08300000 0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, + <&rpmhpd SM8250_CX>; + power-domain-names = "load_state", "cx"; + + memory-region = <&cdsp_mem>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <5>; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8250-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; @@ -1668,6 +1745,45 @@ config { }; }; + adsp: remoteproc@17300000 { + compatible = "qcom,sm8250-adsp-pas"; + reg = <0 0x17300000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, + <&rpmhpd SM8250_LCX>, + <&rpmhpd SM8250_LMX>; + power-domain-names = "load_state", "lcx", "lmx"; + + memory-region = <&adsp_mem>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;
Add remoteproc nodes for the audio, compute and sensor cores, define glink for each one and enable them on the MTP with appropriate firmware defined. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 15 +++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 116 ++++++++++++++++++++++++ 2 files changed, 131 insertions(+)