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[88.207.99.59]) by smtp.googlemail.com with ESMTPSA id 68sm10406912wmz.40.2020.07.02.03.30.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2020 03:30:12 -0700 (PDT) From: Robert Marko To: andrew@lunn.ch, f.fainelli@gmail.com, hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, kuba@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: Robert Marko Subject: [net-next,PATCH 2/4] net: mdio-ipq4019: add clock support Date: Thu, 2 Jul 2020 12:29:59 +0200 Message-Id: <20200702103001.233961-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200702103001.233961-1-robert.marko@sartura.hr> References: <20200702103001.233961-1-robert.marko@sartura.hr> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some newer SoC-s have a separate MDIO clock that needs to be enabled. So lets add support for handling the clocks to the driver. Signed-off-by: Robert Marko --- drivers/net/phy/mdio-ipq4019.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/mdio-ipq4019.c b/drivers/net/phy/mdio-ipq4019.c index 0e78830c070b..7660bf006da0 100644 --- a/drivers/net/phy/mdio-ipq4019.c +++ b/drivers/net/phy/mdio-ipq4019.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -24,8 +25,12 @@ #define IPQ4019_MDIO_TIMEOUT 10000 #define IPQ4019_MDIO_SLEEP 10 +#define QCA_MDIO_CLK_DEFAULT_RATE 100000000 + struct ipq4019_mdio_data { - void __iomem *membase; + void __iomem *membase; + struct clk *mdio_clk; + u32 clk_freq; }; static int ipq4019_mdio_wait_busy(struct mii_bus *bus) @@ -100,6 +105,7 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) { struct ipq4019_mdio_data *priv; struct mii_bus *bus; + struct device_node *np = pdev->dev.of_node; int ret; bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv)); @@ -112,6 +118,26 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) if (IS_ERR(priv->membase)) return PTR_ERR(priv->membase); + priv->mdio_clk = devm_clk_get_optional(&pdev->dev, "mdio_ahb"); + if (!IS_ERR(priv->mdio_clk)) { + if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq)) { + dev_warn(&pdev->dev, "Cannot find MDIO clock frequency, using default!\n"); + priv->clk_freq = QCA_MDIO_CLK_DEFAULT_RATE; + } + + ret = clk_set_rate(priv->mdio_clk, priv->clk_freq); + if (ret) { + dev_err(&pdev->dev, "Cannot set MDIO clock rate!\n"); + return ret; + } + + ret = clk_prepare_enable(priv->mdio_clk); + if (ret) { + dev_err(&pdev->dev, "Cannot enable MDIO clock!\n"); + return ret; + } + } + bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read; bus->write = ipq4019_mdio_write;