@@ -19,6 +19,11 @@ description: |
properties:
compatible:
oneOf:
+ - description: msm9860 TSENS based
+ items:
+ - enum:
+ - qcom,ipq8064-tsens
+
- description: v0.1 of TSENS
items:
- enum:
@@ -47,6 +52,11 @@ properties:
- description: TM registers
- description: SROT registers
+ regmap:
+ description:
+ Phandle to the gcc. On ipq8064 SoCs gcc and tsense share the same regs.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
interrupts:
minItems: 1
items:
@@ -85,12 +95,18 @@ properties:
Number of cells required to uniquely identify the thermal sensors. Since
we have multiple sensors this is set to 1
+required:
+ - compatible
+ - interrupts
+ - "#thermal-sensor-cells"
+
allOf:
- if:
properties:
compatible:
contains:
enum:
+ - qcom,ipq8064-tsens
- qcom,msm8916-tsens
- qcom,msm8974-tsens
- qcom,msm8976-tsens
@@ -111,17 +127,40 @@ allOf:
interrupt-names:
minItems: 2
-required:
- - compatible
- - reg
- - "#qcom,sensors"
- - interrupts
- - interrupt-names
- - "#thermal-sensor-cells"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq8064-tsens
+ then:
+ required:
+ - regmap
+
+ else:
+ required:
+ - reg
+ - interrupt-names
+ - "#qcom,sensors"
additionalProperties: false
examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ // Example msm9860 based SoC (ipq8064):
+ tsens: thermal-sensor {
+ compatible = "qcom,ipq8064-tsens";
+ regmap = <&gcc>;
+
+ nvmem-cells = <&tsens_calib>, <&tsens_calsel>;
+ nvmem-cell-names = "calib", "calib_sel";
+
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
// Example 1 (legacy: for pre v1 IP):
Document the use of regmap phandle for ipq8064 SoCs Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> --- .../bindings/thermal/qcom-tsens.yaml | 53 ++++++++++++++++--- 1 file changed, 46 insertions(+), 7 deletions(-)