Message ID | 20200803193547.305660-13-jcrouse@codeaurora.org (mailing list archive) |
---|---|
State | Superseded |
Headers | show
Return-Path: <SRS0=fprp=BN=vger.kernel.org=linux-arm-msm-owner@kernel.org> Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E90A91575 for <patchwork-linux-arm-msm@patchwork.kernel.org>; Mon, 3 Aug 2020 19:37:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4C20322BF3 for <patchwork-linux-arm-msm@patchwork.kernel.org>; Mon, 3 Aug 2020 19:37:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="fWD4kZ9Z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728555AbgHCThJ (ORCPT <rfc822;patchwork-linux-arm-msm@patchwork.kernel.org>); Mon, 3 Aug 2020 15:37:09 -0400 Received: from mail29.static.mailgun.info ([104.130.122.29]:39977 "EHLO mail29.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728575AbgHCThJ (ORCPT <rfc822;linux-arm-msm@vger.kernel.org>); Mon, 3 Aug 2020 15:37:09 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1596483428; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=yOMYncf5nMXrU1PRqoN8EKXZ0DovQfRsHybdYeETpeQ=; b=fWD4kZ9Zj7QuM+7bPCWyLA+UH48V0HD/5M4LYZzCLVeHmDczp+mWqGy6oAAq1ITWRZ06aX/i Iodk2BIxgtf1OlOVib2MZb98TFzBMDPyV8zB5KJOay73DpKnWIW8kyBvwXNh+4RZqkAfpGAy hCC1DDC7LUgDEMgy/RThuNslVmM= X-Mailgun-Sending-Ip: 104.130.122.29 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n16.prod.us-west-2.postgun.com with SMTP id 5f286748849144fbcbc4eea2 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 03 Aug 2020 19:36:40 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 0A0E8C43469; Mon, 3 Aug 2020 19:36:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=ham autolearn_force=no version=3.4.0 Received: from jordan-laptop.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5C831C43456; Mon, 3 Aug 2020 19:36:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5C831C43456 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse <jcrouse@codeaurora.org> To: linux-arm-msm@vger.kernel.org Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>, Robin Murphy <robin.murphy@arm.com>, Will Deacon <will@kernel.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, freedreno@lists.freedesktop.org, iommu@lists.linux-foundation.org, Andy Gross <agross@kernel.org>, Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 12/12] arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU Date: Mon, 3 Aug 2020 13:35:47 -0600 Message-Id: <20200803193547.305660-13-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803193547.305660-1-jcrouse@codeaurora.org> References: <20200803193547.305660-1-jcrouse@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: <linux-arm-msm.vger.kernel.org> X-Mailing-List: linux-arm-msm@vger.kernel.org |
Series |
iommu/arm-smmu: Add Adreno SMMU specific implementation
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expand
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diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2884577dcb77..6a9adaa401a9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4058,7 +4058,7 @@ opp-257000000 { }; adreno_smmu: iommu@5040000 { - compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; + compatible = "qcom,adreno-smmu", "qcom,smmu-v2"; reg = <0 0x5040000 0 0x10000>; #iommu-cells = <1>; #global-interrupts = <2>;
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable split pagetables and per-instance pagetables for drm/msm. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)