Message ID | 20200810222657.1841322-7-jcrouse@codeaurora.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show
Return-Path: <SRS0=rfUr=BU=vger.kernel.org=linux-arm-msm-owner@kernel.org> Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2EE92739 for <patchwork-linux-arm-msm@patchwork.kernel.org>; Mon, 10 Aug 2020 22:28:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 16A522075D for <patchwork-linux-arm-msm@patchwork.kernel.org>; Mon, 10 Aug 2020 22:28:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="ttcW1DBk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727024AbgHJW1X (ORCPT <rfc822;patchwork-linux-arm-msm@patchwork.kernel.org>); Mon, 10 Aug 2020 18:27:23 -0400 Received: from mail29.static.mailgun.info ([104.130.122.29]:35273 "EHLO mail29.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727021AbgHJW1X (ORCPT <rfc822;linux-arm-msm@vger.kernel.org>); Mon, 10 Aug 2020 18:27:23 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1597098442; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=GrEw3oSw++nMPzEl+/BHJDxleP5vanw4s1YWFdwf0mU=; b=ttcW1DBkqZFxWQhu9vWGGik7RDpPvQnR6tOAelQWeyeShOVSrXkd4Q19Eu7R1R5hYRIRBoQ8 /kIuEZlqcHC5TqkvvcEdo2DyFNS24uHtUb85FlCNShgzflSnMeVvtYjM4aePCwATs/77+UMw 8dNup8FdSpa7t4i4bzp0crSeeVQ= X-Mailgun-Sending-Ip: 104.130.122.29 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-west-2.postgun.com with SMTP id 5f31c9cac85a1092b0faef36 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 10 Aug 2020 22:27:22 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 658CAC433B2; Mon, 10 Aug 2020 22:27:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from jordan-laptop.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7E7E2C433C9; Mon, 10 Aug 2020 22:27:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7E7E2C433C9 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse <jcrouse@codeaurora.org> To: linux-arm-msm@vger.kernel.org Cc: Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, Bjorn Andersson <bjorn.andersson@linaro.org>, iommu@lists.linux-foundation.org, freedreno@lists.freedesktop.org, Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>, Rob Herring <robh@kernel.org>, Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v12 06/13] dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU Date: Mon, 10 Aug 2020 16:26:50 -0600 Message-Id: <20200810222657.1841322-7-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200810222657.1841322-1-jcrouse@codeaurora.org> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: <linux-arm-msm.vger.kernel.org> X-Mailing-List: linux-arm-msm@vger.kernel.org |
Series |
iommu/arm-smmu: Add Adreno SMMU specific implementation
|
expand
|
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 503160a7b9a0..70996348c1d8 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -49,6 +49,10 @@ properties: - enum: - nvidia,tegra194-smmu - const: nvidia,smmu-500 + - description: Qcom Adreno GPUs implementing "arm,smmu-v2" + items: + - const: qcom,adreno-smmu + - const: qcom,smmu-v2 - items: - const: arm,mmu-500 - const: arm,smmu-v2