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[3/5] dt-bindings: clock: add SM8250 QCOM video clock bindings

Message ID 20200902031359.6703-4-jonathan@marek.ca (mailing list archive)
State Superseded
Headers show
Series SM8150 and SM8250 videocc drivers | expand

Commit Message

Jonathan Marek Sept. 2, 2020, 3:13 a.m. UTC
Add device tree bindings for video clock controller for SM8250 SoCs.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 .../bindings/clock/qcom,videocc.yaml          |  6 ++-
 .../dt-bindings/clock/qcom,videocc-sm8250.h   | 42 +++++++++++++++++++
 2 files changed, 47 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8250.h

Comments

Rob Herring (Arm) Sept. 3, 2020, 4:12 p.m. UTC | #1
On Tue, 01 Sep 2020 23:13:53 -0400, Jonathan Marek wrote:
> Add device tree bindings for video clock controller for SM8250 SoCs.
> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
>  .../bindings/clock/qcom,videocc.yaml          |  6 ++-
>  .../dt-bindings/clock/qcom,videocc-sm8250.h   | 42 +++++++++++++++++++
>  2 files changed, 47 insertions(+), 1 deletion(-)
>  create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8250.h
> 


My bot found errors running 'make dt_binding_check' on your patch:

/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,videocc.example.dt.yaml: clock-controller@ab00000: clocks: [[4294967295, 0]] is too short
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,videocc.example.dt.yaml: clock-controller@ab00000: clock-names: ['bi_tcxo'] is too short
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,videocc.yaml


See https://patchwork.ozlabs.org/patch/1355500

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:

pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade

Please check and re-submit.
Rob Herring (Arm) Sept. 3, 2020, 4:13 p.m. UTC | #2
On Tue, Sep 01, 2020 at 11:13:53PM -0400, Jonathan Marek wrote:
> Add device tree bindings for video clock controller for SM8250 SoCs.

WARNING: please, no space before tabs
#182: FILE: include/dt-bindings/clock/qcom,videocc-sm8250.h:37:
+#define MVS0C_GDSC ^I^I^I0$

WARNING: please, no space before tabs
#183: FILE: include/dt-bindings/clock/qcom,videocc-sm8250.h:38:
+#define MVS1C_GDSC ^I^I^I1$

WARNING: please, no space before tabs
#184: FILE: include/dt-bindings/clock/qcom,videocc-sm8250.h:39:
+#define MVS0_GDSC ^I^I^I2$

WARNING: please, no space before tabs
#185: FILE: include/dt-bindings/clock/qcom,videocc-sm8250.h:40:
+#define MVS1_GDSC ^I^I^I3$

total: 0 errors, 4 warnings, 73 lines checked


> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
>  .../bindings/clock/qcom,videocc.yaml          |  6 ++-
>  .../dt-bindings/clock/qcom,videocc-sm8250.h   | 42 +++++++++++++++++++
>  2 files changed, 47 insertions(+), 1 deletion(-)
>  create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8250.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
> index d04f5bd28dde..757837e260a2 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
> @@ -11,12 +11,13 @@ maintainers:
>  
>  description: |
>    Qualcomm video clock control module which supports the clocks, resets and
> -  power domains on SDM845/SC7180/SM8150.
> +  power domains on SDM845/SC7180/SM8150/SM8250.
>  
>    See also:
>      dt-bindings/clock/qcom,videocc-sdm845.h
>      dt-bindings/clock/qcom,videocc-sc7180.h
>      dt-bindings/clock/qcom,videocc-sm8150.h
> +    dt-bindings/clock/qcom,videocc-sm8250.h
>  
>  properties:
>    compatible:
> @@ -24,14 +25,17 @@ properties:
>        - qcom,sdm845-videocc
>        - qcom,sc7180-videocc
>        - qcom,sm8150-videocc
> +      - qcom,sm8250-videocc
>  
>    clocks:
>      items:
>        - description: Board XO source
> +      - description: Board XO source, always-on (required by sm8250 only)
>  
>    clock-names:
>      items:
>        - const: bi_tcxo
> +      - const: bi_tcxo_ao
>  
>    '#clock-cells':
>      const: 1
> diff --git a/include/dt-bindings/clock/qcom,videocc-sm8250.h b/include/dt-bindings/clock/qcom,videocc-sm8250.h
> new file mode 100644
> index 000000000000..4c44f9c468db
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,videocc-sm8250.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
> +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
> +
> +/* VIDEO_CC clocks */
> +#define VIDEO_CC_AHB_CLK		0
> +#define VIDEO_CC_AHB_CLK_SRC		1
> +#define VIDEO_CC_MVS0_CLK		2
> +#define VIDEO_CC_MVS0_CLK_SRC		3
> +#define VIDEO_CC_MVS0_DIV_CLK_SRC	4
> +#define VIDEO_CC_MVS0C_CLK		5
> +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC	6
> +#define VIDEO_CC_MVS1_CLK		7
> +#define VIDEO_CC_MVS1_CLK_SRC		8
> +#define VIDEO_CC_MVS1_DIV2_CLK		9
> +#define VIDEO_CC_MVS1_DIV_CLK_SRC	10
> +#define VIDEO_CC_MVS1C_CLK		11
> +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC	12
> +#define VIDEO_CC_XO_CLK			13
> +#define VIDEO_CC_XO_CLK_SRC		14
> +#define VIDEO_CC_PLL0			15
> +#define VIDEO_CC_PLL1			16
> +
> +/* VIDEO_CC resets */
> +#define VIDEO_CC_CVP_INTERFACE_BCR	0
> +#define VIDEO_CC_CVP_MVS0_BCR		1
> +#define VIDEO_CC_MVS0C_CLK_ARES		2
> +#define VIDEO_CC_CVP_MVS0C_BCR		3
> +#define VIDEO_CC_CVP_MVS1_BCR		4
> +#define VIDEO_CC_MVS1C_CLK_ARES		5
> +#define VIDEO_CC_CVP_MVS1C_BCR		6
> +
> +#define MVS0C_GDSC 			0
> +#define MVS1C_GDSC 			1
> +#define MVS0_GDSC 			2
> +#define MVS1_GDSC 			3
> +
> +#endif
> -- 
> 2.26.1
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
index d04f5bd28dde..757837e260a2 100644
--- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
@@ -11,12 +11,13 @@  maintainers:
 
 description: |
   Qualcomm video clock control module which supports the clocks, resets and
-  power domains on SDM845/SC7180/SM8150.
+  power domains on SDM845/SC7180/SM8150/SM8250.
 
   See also:
     dt-bindings/clock/qcom,videocc-sdm845.h
     dt-bindings/clock/qcom,videocc-sc7180.h
     dt-bindings/clock/qcom,videocc-sm8150.h
+    dt-bindings/clock/qcom,videocc-sm8250.h
 
 properties:
   compatible:
@@ -24,14 +25,17 @@  properties:
       - qcom,sdm845-videocc
       - qcom,sc7180-videocc
       - qcom,sm8150-videocc
+      - qcom,sm8250-videocc
 
   clocks:
     items:
       - description: Board XO source
+      - description: Board XO source, always-on (required by sm8250 only)
 
   clock-names:
     items:
       - const: bi_tcxo
+      - const: bi_tcxo_ao
 
   '#clock-cells':
     const: 1
diff --git a/include/dt-bindings/clock/qcom,videocc-sm8250.h b/include/dt-bindings/clock/qcom,videocc-sm8250.h
new file mode 100644
index 000000000000..4c44f9c468db
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sm8250.h
@@ -0,0 +1,42 @@ 
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK		0
+#define VIDEO_CC_AHB_CLK_SRC		1
+#define VIDEO_CC_MVS0_CLK		2
+#define VIDEO_CC_MVS0_CLK_SRC		3
+#define VIDEO_CC_MVS0_DIV_CLK_SRC	4
+#define VIDEO_CC_MVS0C_CLK		5
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC	6
+#define VIDEO_CC_MVS1_CLK		7
+#define VIDEO_CC_MVS1_CLK_SRC		8
+#define VIDEO_CC_MVS1_DIV2_CLK		9
+#define VIDEO_CC_MVS1_DIV_CLK_SRC	10
+#define VIDEO_CC_MVS1C_CLK		11
+#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC	12
+#define VIDEO_CC_XO_CLK			13
+#define VIDEO_CC_XO_CLK_SRC		14
+#define VIDEO_CC_PLL0			15
+#define VIDEO_CC_PLL1			16
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_CVP_INTERFACE_BCR	0
+#define VIDEO_CC_CVP_MVS0_BCR		1
+#define VIDEO_CC_MVS0C_CLK_ARES		2
+#define VIDEO_CC_CVP_MVS0C_BCR		3
+#define VIDEO_CC_CVP_MVS1_BCR		4
+#define VIDEO_CC_MVS1C_CLK_ARES		5
+#define VIDEO_CC_CVP_MVS1C_BCR		6
+
+#define MVS0C_GDSC 			0
+#define MVS1C_GDSC 			1
+#define MVS0_GDSC 			2
+#define MVS1_GDSC 			3
+
+#endif