| Message ID | 20200929001925.2916984-1-robdclark@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 200a2186b62714c099693dcb6444af373eaabf62 |
| Headers | show |
| Series | drm/msm: fix 32b build warns | expand |
On 2020-09-28 17:19, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > Neither of these code-paths apply to older 32b devices, but it is rude > to introduce warnings. > > Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- > drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > index fd8f491f2e48..458b5b26d3c2 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -209,7 +209,7 @@ adreno_iommu_create_address_space(struct msm_gpu > *gpu, > size = iommu->geometry.aperture_end - start + 1; > > aspace = msm_gem_address_space_create(mmu, "gpu", > - start & GENMASK(48, 0), size); > + start & GENMASK_ULL(48, 0), size); > > if (IS_ERR(aspace) && !IS_ERR(mmu)) > mmu->funcs->destroy(mmu); > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > index 029cc8bf5a04..de0dfb815125 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > @@ -879,7 +879,7 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct > platform_device *pdev, int id) > pll->max_rate = 3500000000UL; > if (pll->type == MSM_DSI_PHY_7NM_V4_1) { > pll->min_rate = 600000000UL; > - pll->max_rate = 5000000000UL; > + pll->max_rate = (unsigned long)5000000000ULL; > /* workaround for max rate overflowing on 32-bit builds: */ > pll->max_rate = max(pll->max_rate, 0xffffffffUL); > }
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index fd8f491f2e48..458b5b26d3c2 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -209,7 +209,7 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, size = iommu->geometry.aperture_end - start + 1; aspace = msm_gem_address_space_create(mmu, "gpu", - start & GENMASK(48, 0), size); + start & GENMASK_ULL(48, 0), size); if (IS_ERR(aspace) && !IS_ERR(mmu)) mmu->funcs->destroy(mmu); diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c index 029cc8bf5a04..de0dfb815125 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c @@ -879,7 +879,7 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) pll->max_rate = 3500000000UL; if (pll->type == MSM_DSI_PHY_7NM_V4_1) { pll->min_rate = 600000000UL; - pll->max_rate = 5000000000UL; + pll->max_rate = (unsigned long)5000000000ULL; /* workaround for max rate overflowing on 32-bit builds: */ pll->max_rate = max(pll->max_rate, 0xffffffffUL); }